15
FN9223.1
July 28, 2008
dissipated in the lower MOSFET can be found in
Equation 15.
where: I
M
is the maximum continuous output current, I
L,P-P
is the peak-to-peak inductor current, and D is the duty cycle
(approximately V
OUT
/V
IN
).
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
M
, V
D(ON)
; the switching
frequency, f
S
; and the length of dead times, t
d1
and t
d2
, at
the beginning and the end of the lower-MOSFET conduction
interval, respectively.
Equation 16 assumes the current through the lower
MOSFET is always positive; if so, the total power dissipated
in each lower MOSFET is approximated by the summation of
P
LMOS1
and P
LMOS2
.
UPPER MOSFET POWER CALCULATION
In addition to r
DS(ON)
losses, a large portion of the upper
MOSFET losses are switching losses, due to currents
conducted through the device while the input voltage is
present as V
DS
. Upper MOSFET losses can be divided into
separate components, separating the upper MOSFET
switching losses, the lower MOSFET body diode reverse
recovery charge loss, and the upper MOSFET r
DS(ON)
conduction loss.
In most typical circuits, when the upper MOSFET turns off, it
continues to conduct the inductor current until the voltage at
the phase node falls below ground. Once the lower
MOSFET begins conducting (via its body diode or
enhancement channel), the current in the upper MOSFET
falls to zero. In the following equation, the required time for
this commutation is t
1
and the associated power loss is
P
UMOS,1
.
Similarly, the upper MOSFET begins conducting as soon as
it begins turning on. Assuming the inductor current is in the
positive domain, the upper MOSFET sees approximately the
input voltage applied across its drain and source terminals,
while it turns on and starts conducting the inductor current.
This transition occurs over a time t
2
, and the approximate
the power loss is P
UMOS,2
.
A third component involves the lower MOSFET’s
reverse-recovery charge, Q
RR
. Since the lower MOSFET’s
body diode conducts the full inductor current before it has
fully switched to the upper MOSFET, the upper MOSFET
has to provide the charge required to turn off the lower
MOSFET’s body diode. This charge is conducted through
the upper MOSFET across VIN, the power dissipated as a
result, P
UMOS,3
can be approximated as shown in
Equation 19.
Lastly, the conduction loss part of the upper MOSFET’s
power dissipation, P
UMOS,4,
can be calculated using
Equation 20.
In this case, of course, r
DS(ON)
is the ON-resistance of the
upper MOSFET.
The total power dissipated by the upper MOSFET at full load
can be approximated as the summation of these results.
Since the power equations depend on MOSFET parameters,
choosing the correct MOSFETs can be an iterative process
that involves repetitively solving the loss equations for
different MOSFETs and different switching frequencies until
converging upon the best solution.
OUTPUT FILTER DESIGN
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the square
wave voltage at the phase nodes. Additionally, the output
capacitors must also provide the energy required by a fast
transient load during the short interval of time required by the
controller and power train to respond. Because it has a low
bandwidth compared to the switching frequency, the output
filter limits the system transient response leaving the output
capacitor bank to supply the load current or sink the inductor
currents, all while the current in the output inductors
increases or decreases to meet the load demand.
In high-speed converters, the output capacitor bank is
amongst the costlier (and often the physically largest) parts
of the circuit. Output filter design begins with consideration
of the critical load parameters: maximum size of the load
step, I, the load-current slew rate, di/dt, and the maximum
allowable output voltage deviation under transient loading,
V
MAX
. Capacitors are characterized according to their
capacitance, ESR, and ESL (equivalent series inductance).
P
LMOS1
r
DS ON
I
OUT
2
-------------
2
1D–
I
L
P-P,
2
1D–
12
----------------------------------
+=
(EQ. 15)
P
LMOS 2
V
DON
f
S
I
OUT
2
-------------
I
P-P
2
-----------
+
t
d1
I
OUT
2
-------------
I
P-P
2
-----------
–
t
d2
+
=
(EQ. 16)
P
UMOS 1,
V
IN
I
OUT
N
-------------
I
L
P-P,
2
---------------
+
t
1
2
----
f
S
(EQ. 17)
P
UMOS 2,
V
IN
I
OUT
N
-------------
I
L
P-P,
2
---------------
–
t
2
2
----
f
S
(EQ. 18)
P
UMOS 3,
V
IN
Q
rr
f
S
=
(EQ. 19)
P
UMOS 4,
r
DS ON
d
I
OUT
N
-------------
2
I
P-P
2
12
-----------
+=
(EQ. 20)
ISL8101ISL8101
