AT17F16A-30JU Datasheet AT17F16A-30JU | P1-P3

Features

• Programmable 16, 777, 216 x 1-bit Serial Memories Designed to Store Configuration

Programs for Field Programmable Gate Arrays (FPGAs)

• 3.3V Output Capability

• 5V Tolerant I/O Pins

• Program Support using the Atmel ATDH2200E System or Industry Third-party

Programmers

• In-System Programmable (ISP) via 2-wire Bus

• Simple Interface to SRAM FPGAs

• Compatible with Atmel AT40K and AT94K Devices, Altera

FLEX

, Excalibur

™

, Stratix

Cyclone

™

and APEX

™

Devices

• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays

• Low-power CMOS FLASH Process

• Available in 8-lead LAP and 20-lead PLCC Packages

• Emulation of Atmel’s AT24CXXX Serial EEPROMs

• Low-power Standby Mode

• Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System

Reconfiguration

• Fast Serial Download Speeds up to 33 MHz

• Endurance: 10,000 Write Cycles Typical

• Green (Pb/Halide-free/RoHS Compliant) Packages

1. Description

The AT17FxxA Series of In-System Programmable Configuration PROMs (Configura-

tors) provide an easy-to-use, cost-effective configuration memory for Field

Programmable Gate Arrays. The AT17FxxA Series device is packaged in the 8-lead

LAP and 20-lead PLCC, see Table 1-1. The AT17FxxA Series Configurator uses a

simple serial-access procedure to configure one or more FPGA devices.

The AT17FxxA Series Configurators can be programmed with industry-standard pro-

grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

Table 1-1. AT17FxxA Series Packages

Package AT17F16A

8-lead LAP Yes

20-lead PLCC Yes

FPGA

Configuration

Flash Memory

AT17F16A

3474E–CNFG–2/08

AT17F16A

2. Pin Configuration

8-lead LAP

20-lead PLCC

DATA

DCLK

RESET/OE

nCS

VCC

SER_EN

(A2) nCASC

GND

DCLK

PAGESEL1

RESET/OE

SER_EN

PAGE_EN

READY

nCS

GND

PAGESEL0

(A2) nCASC

DATA

VCC

3474E–CNFG–2/08

AT17F16A

3. Block Diagram

4. Device Description

The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface

directly with the FPGA device control signals. All FPGA devices can control the entire configura-

tion process and retrieve data from the configuration device without requiring an external

intelligent controller.

The RESET

/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the

address counter. When RESET/OE is driven Low, the configuration device resets its address

counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17FxxA

Series Configurator. If nCS is held High after the RESET

/OE reset pulse, the counter is disabled

and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the

DATA output pin are enabled. When RESET

/OE is driven Low again, the address counter is

reset and the DATA output pin is tri-stated, regardless of the state of nCS.

When the configurator has driven out all of its data and nCASC is driven Low, the device tri-

states the DATA pin to avoid contention with other configurators. Upon power-up, the address

counter is automatically reset.

Config. Page

Select

Power-on

Reset

Flash

Memory

Clock/Oscillator

Logic

2-wire Serial Programming

Serial Download Logic

Control Logic

DCLK

nCASC(A2)

DATA

nCS

RESET/OE

SER_EN

CE/WE/OE

Data

Address

READY

PAGE_EN

PAGESEL0

PAGESEL1

Reset

Config. Page

Select

Power-on

Reset

Flash

Memory

Clock/Oscillator

Logic

2-wire Serial Programming

Serial Download Logic

Control Logic

DCLK

nCASC(A2)

DATA

nCS

RESET/OE

SER_EN

CE/WE/OE

Data

Address

READY

PAGE_EN

PAGESEL0

PAGESEL1

Reset

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

AT17F16A-30JU

Mfr. #:

Buy AT17F16A-30JU

Manufacturer:

Microchip Technology / Atmel

Description:

FPGA - Configuration Memory SER CONFIG FLASH-16M ALTERA PINOUT-30MHZ

Lifecycle:

New from this manufacturer.

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AT17F16A-30JU