The MISO pin on the QT floats in 3-state mode between bytes
when /SS is high. This facilitates multiple devices on one SPI
bus.
Null Bytes: When the QT responds to a command with one
or more response bytes, the host can issue a new command
to the QT instead of a null in the last shift operation.
New commands attempted during intermediate byte transfers
are ignored, and null bytes should always be used in these
cases.
3.3 UART Communications
See also SR setup parameter, page 16.
UART mode is selected if the host sends data over the UART
lines first. There is no other configuration required to make
the device operate in UART mode. Once UART is selected
after a power-up, the device cannot switch to SPI mode
unless the device is reset.
UART mode communications functions in the same basic way
as SPI communications. The Baud rate is adjusted by means
of setup parameter ‘SR’ (pages 16, 0). Once a new Baud rate
has been set, the device must be reset for the new rate to
take effect.
The major difference with SPI mode is that the UART mode is
asynchronous and so the host does not clock the QT. No
framing /SS or clock signal is required, simplifying the
interface greatly. Return data is sent from the QT back to the
host when the data is ready.
Multi-drop capability: The QT60xx6 in UART mode floats Tx
within 10µs after each transmitted byte. The host’s Rx pin can
thus be shared with other similar UART based peripherals.
Wake operation: The device can be put into sleep mode with
a serial command, 0x16 (page 9) and then be waked with a
dummy null byte from the host, if the Rx and WS pins are
connected together.
Rx - Receive async data. This pin is an input only.
Tx - Transmit async data. Drives out when transmitting but
floats within 10
µ
s of the end of the stop bit, to allow
bussing with several similar parts. Tx should idle high, and
must be pulled high with a 10K ~ 20K resistor to Vdd at all
times in UART mode. Tx is push-pull when transmitting
data.
UART transmission parameters are:
Baud rate: 9600 ~ 115,200
Start bits: 1
Data bits: 8
Parity: None
Stop bits: 1
DRDY in UART mode: Section 3.1 applies.
DRDY is bi-directional in UART mode. DRDY can be pulled
down by either the QT or the host (wire-AND), so that either
device can be inhibited from sending data until the other is
ready. The host should obey this control line or transmission
errors can occur. The host should grant a 10µs grace period
after clamping DRDY low in which it can still accept a
transmission.
As explained in Section 3.1, DRDY is not clamped low
immediately after the QT receives a byte; there can be up to a
100µs delay from the end of the stop bit before DRDY goes
low. Sampling of DRDY by the host should occur 100µs after
the byte has been fully sent; if DRDY is already high at this
point, or becomes high, then it is clear to send.
Null Bytes: Unlike SPI mode, there is no reason to send null
bytes to the QT in UART mode.
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7 QT60486-AS 0.07/1103
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Figure 3-3 UART Connections
Rx Tx
DRDY
Tx
P_IN
Host MCU QT60xx6
V
d
d
10K
Rx
Vdd
10K
4 Control Commands
Refer to Section 5.1, page 11 for further details.
The devices feature a set of commands which are used for
control and status reporting. The host device has to send the
command to the QT60xx6 and await a response.
SPI mode: While waiting the host should delay for 100 µs
from the end of the command, then start to check if DRDY is
or goes high. If it is high, then the host master can clock out
the resulting byte(s).
UART mode: After the command is sent, the QT will send
back the response usually starting within 100µs. The host can
clamp DRDY low (wire-AND logic) to inhibit a response if the
host is not able to receive the transmission.
4.1 Null Command - 0x00
Used primarily to shift back data from the QT in SPI mode.
Since the host device is always the master in SPI mode, and
data is clocked in both directions, the Null command is
required frequently to act as a placeholder where the desire is
to only get data back from the QT, not to send it.
In SPI communications, when the QT60xx6 responds to a
command with one or more response bytes, the host can
issue a new command instead of a null on the last byte shift
operation.
New commands during intermediate byte shift-out operations
are ignored, and null bytes should always be used.
4.2 Enter Setups Mode - 0x01
This command is used to initiate the Setups block transfer
from Host to QT.
The command must be repeated 2x within 100ms or the
command will fail; the repeating command must be sequential
without any intervening command. After the 2nd 0x01 from
the host, the QT will reply with the character 0xFE. In SPI
mode this character must be shifted out by sending a null
(0x00) from the host. This command suspends normal
sensing starting from the first 0x01. A failure of the command
will cause a timeout.
Each byte in the block must arrive at the QT no later than
100ms after the previous one or a timeout will occur.
Any timeout will cause the device to cancel the block load and
go back to normal operation.
If no response comes back, the command was not received
and the device should preferably be reset from the host by
hardware reset just in case there are any other problems.
If 0xFE is received by the host, then the host should begin to
transmit the block of Setups to the QT. DRDY handshakes the
data. The delay between bytes can be as short as 10us but
the host can make it longer than this if required, but no more
than 100ms. The last two bytes the host should send is the
CRC for the block of data only.
After the block transfer the QT will check the CRC and
respond with 0x00 if there was an error. Regardless, it will
program the internal eeprom. If the CRC was correct it will
reply with a second 0xFE after the eeprom was programmed.
If there was an error in the block transfer the device will
restore the last known good Setups from Flash memory the
next time the device is reset. However until that point, the
device will attempt to operate using the new Setups block
even if it is corrupt.
At the end of the full block load sequence, the device restarts
sensing without recalibration.
4.3 Cal All - 0x03
This command must be repeated 2x within 100ms or the
command will fail; the repeating command must be sequential
without any intervening command.
After the 2nd 0x03 from the host, the QT will reply with the
character 0xFC. Shortly thereafter the device will recalibrate
all keys and restart operation.
If no 0xFC comes back, the command was not properly
received and the device should preferably be reset.
The host can monitor the progress of the recalibration by
checking the status byte, using command 0x05.
4.4 Force Reset - 0x04
The command must be repeated 2x within 100ms or the
command will fail; the repeating command must be sequential
without any intervening command. After the 2nd 0x04, the QT
will reply with the character 0xFB just prior to executing the
reset operation.
The host can monitor the progress of the reset by checking
the status byte for recalibration, using command 0x05.
4.5 Error Status - 0x05
This command returns the general error status code.
Bit 5: Set if there is a FMEA failure detected
Bit 6: Set of there is a communications failure. This can be
reset by sending command 0x0f (last command command).
A CRC byte is appended to the response; this CRC folds in
the command 0x05 itself initially.
4.6 Report 1st Key - 0x06
Reports the first or only key to be touched, plus indicates if
there are yet other keys that are also touched.
The return bits are as follows:
Key bit 0
0
Key bit 1
1
Key bit 2
2
Key bit 3
3
Key bit 4
4
Key bit 5
5
1= any error condition is present
6
1= more than 1 key is active
7
DescriptionBIT
Bits 0..5 encode for the first detected key in range 0..47.
If 2 or more keys in detection, bit 7 is set and the host should
interrogate the part via the 0x07 command to read out all the
key detections. This one command should be the dominant
interrogation command in the host interface; further
commands can be issued if the response to 0x06 warrants it.
A CRC byte is appended to the response; this CRC folds in
the command 0x06 itself initially.
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4.7 Report Detections for All Keys - 0x07
Returns six bytes which indicate all keys in detection if any,
as a bitfield. The first byte returned is the MSByte. Key 0
reports in LSByte bit 0.
A CRC byte is appended to the response; this CRC folds in
the command 0x07 itself initially.
4.8 Report Signals for All Keys - 0x08
Returns the raw signal values for all keys. Each value is a
16-bit number, and there are 48 words returned. No CRC is
appended to the return, so the data should not be considered
secure. The high byte of key 0 is returned first.
4.9 Report References for All Keys - 0x09
Returns the reference values for all keys. Each value is a
16-bit number, and there are 48 words returned. No CRC is
appended to the return, so the data should not be considered
secure. The high byte of key 0 is returned first.
4.10 Report Deltas for All Keys - 0x0a
Returns the delta signal values with respect to the reference
levels for all keys. Each value is an 8-bit signed number, and
there are 48 bytes returned. No CRC is appended to the
return, so the data should not be considered secure. The
byte for key 0 is returned first.
If the delta value exceeds the range -127 ... +128, the result is
truncated.
4.11 Report Error Flags for All Keys - 0x0b
Returns six bytes which show error flags as a bitfield for all
keys. The first byte returned is the MSByte. Key 0 reports in
LSByte bit 0.
A CRC byte is appended to the response; this CRC folds in
the command 0x0b itself initially.
4.12 Report FMEA Status - 0x0c
Returns one byte which shows the FMEA error status of the X
and Y matrix scan lines, OR’d together in one result byte.
Each bit in the byte represents the OR of one X and one Y
scan line (except for the top two bits which are X only). A one
in any bit position indicates an error in a corresponding scan
line.
A CRC byte is appended to the response; this CRC folds in
the command 0x0c itself initially.
4.13 Dump Setups Block - 0x0d
This command causes the device to dump the entire internal
Setups block back to the host.
If the transfer is not paced faster than 100ms per byte the
transfer will be aborted and the device will time out. This can
happen if the host is also controlling DRDY.
During the transfer, sensing is halted. Sensing is resumed
after the command has finished.
A 16-bit CRC is appended to the response; this CRC is the
same as the Setups table CRC and is sent LSByte first.
4.14 Eeprom CRC - 0x0e
This command returns the 16-bit CRC calculated from the
eeprom contents. The CRC is sent back LSByte first. The
CRC sent back is the same CRC that is appended to the end
of the Setups block.
No CRC is appended to the response.
4.15 Return Last Command - 0x0f
This command returns the last received command character,
in 1’s complement (inverted). If the command is repeated
twice or more, it will return the inversion of 0x0f, 0xf0.
If a prior command was not valid or was corrupted, it will
return the bad command as well.
No CRC is appended to the response.
4.16 Version - 0x10
This command returns the version number of the part as a
value from 0..255.
A CRC byte is appended to the response; this CRC folds in
the command 0x10 itself initially.
4.17 Internal Code - 0x11
This command returns an internal code word (2 bytes) of the
part for factory diagnostic purposes.
A CRC byte is appended to the response; this CRC folds in
the command 0x11 itself initially.
4.18 Internal Code - 0x12
This command returns an internal code word (2 bytes) of the
part for factory diagnostic purposes.
No CRC is appended to the response.
4.19 Sleep - 0x16
The command must be repeated 2x within 100ms or the
command will fail. After the 2nd 0x16 from the host, the
device will reply with the character 0xe9 then sleep.
The device will then enter a lower power sleep mode until
awakened by an edge or pulse on pin WS. When the device
wakes, it will resume current operation in the state from which
it exited and attempt to send a 0x01 code back to the host.
During Sleep the DRDY pin is held low, and released once
the device awakes and is ready to return the 0x01 code.
The WS pin can be connected to Rx or /SS to provide a ‘free’
wakeup connection from the host controller. A dummy byte or
/SS toggle can be sent to wake up the device.
4.20 Data Set for One Key - 0x4k
Returns the data set for key k, where k = {0..47}. This returns
5 bytes, in the sequence:
Signal (2 bytes)
Reference (2 bytes)
Normal Detect Integrator (1 byte)
Signal and Reference are returned LSByte first.
No CRC is appended.
4.21 Status for Key ‘k’ - 0x8k
Returns a bitfield for key ‘k’ where k is from {0..47}. The
bitfield indicates as follows:
Bit 4: Set if key is enabled
Bit 3: Set if key is in detect
Bit 2: Set if the key’s reference is less than LSL
A CRC byte is appended to the response; this CRC folds in
the command 0x8k itself initially.
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9 QT60486-AS 0.07/1103
Advanced information; subject to change

QT60486-AS

Mfr. #:
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Description:
SENSOR IC MTRX TOUCH48KEY 44TQFP
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