CY7C128A
Document #: 38-05028 Rev. ** Page 3 of 10
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
Ω
R2
255
Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤ 5ns
≤ 5 ns
5V
OUTPUT
C128A–4
R1 481Ω
R2
255
Ω
5pF
INCLUDING
JIG AND
SCOPE
C128A–5
(a) (b)
OUTPUT 1.73V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
167
Ω
Switching Characteristics Over the Operating Range
[2, 6]
7C128A-15 7C128A-20 7C128A-25 7C128A-35 7C128A-45
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 15 20 25 35 45 ns
t
AA
Address to Data Valid 15 20 25 35 45 ns
t
OHA
Data Hold from Address Change 5 5 5 5 5 ns
t
ACE
CE LOW to Data Valid 15 20 25 35 45 ns
t
DOE
OE LOW to Data Valid 10 10 12 15 20 ns
t
LZOE
OE LOW to Low Z 3 3 3 3 3 ns
t
HZOE
OE HIGH to High Z
[7]
8 8 10 12 15 ns
t
LZCE
CE LOW to Low Z
[8]
55555ns
t
HZCE
CE HIGH to High Z
[7, 8]
8 8 10 15 15 ns
t
PU
CE LOW to Power-Up 0 0 0 0 0 ns
t
PD
CE HIGH to Power-Down 15 20 20 20 25 ns
WRITE CYCLE
[9]
t
WC
Write Cycle Time 15 20 20 25 40 ns
t
SCE
CE LOW to Write End 1215202530ns
t
AW
Address Set-Up to Write End1215202530ns
t
HA
Address Hold from Write End 0 0 0 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 0 0 0 ns
t
PWE
WE Pulse Width 1215152020ns
t
SD
Data Set-Up to Write End1010101515ns
t
HD
Data Hold from Write End 0 0 0 0 0 ns
t
HZWE
WE LOW to High Z
[7]
7771015ns
t
LZWE
WE HIGH to Low Z 5 5 5 5 5 ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
9. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
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