LTC2756
8
2756fa
For more information www.linear.com/LTC2756
pin FuncTions
R
OFS
(Pin 1): Bipolar Offset Resistor. This pin provides the
translation of the output voltage range for bipolar spans.
Accepts up to ±15V; for normal operation tie to the posi
-
tive reference voltage at R
IN
(Pin 5).
REF (Pin 2): DAC Reference Input, and Feedback Resistor
for the Reference Inverting Amplifier. The external reference
inverting amplifier sees as its load the 10k DAC reference
input resistance in parallel with the 20k feedback resis
-
tor. For normal operation tie this pin to the output of the
reference inverting amplifier (see the T
ypical Applications
section). T
ypically 5V; accepts up to ±15V.
R
COM
(Pin 3): Virtual Ground Point for the On-Chip Refer-
ence Inverting Resistors. These precision-matched 20k
resistors are
included on the chip to facilitate generation
of the negative reference voltage needed to produce a
positive output polarity. They are connected internally from
R
IN
to R
COM
and from R
COM
to REF (see Block Diagram).
For normal operation tie R
COM
to the negative input of
the external reference inverting amplifier (see the Typical
Applications section).
GE
ADJA
(Pin 4): Gain Adjust Pin. This control pin can be
used to null gain error or to compensate for reference
errors. Nominal adjustment range is ±2048 LSB for a
voltage input range of ±V
RIN
(i.e., ±5V for a 5V reference
input). Tie to ground if not used.
R
IN
(Pin 5): Input Resistor for Reference Inverting Ampli-
fier. The 20k input resistor is connected internally from
R
IN
to R
COM
. For normal operation tie R
IN
to the external
reference voltage (see the Typical Applications section).
Typically 5V; accepts up to ±15V.
GND (Pins 6, 8, 13, 15, 16, 24): Ground; tie to ground.
I
OUT2
(Pin 7): Current Output Complement. Tie to ground
via a clean, low-impedance path.
CS/LD (Pin 9): Synchronous Chip Select and Load Input
Pin. A logic low on this pin enables SDI, SCK and SRO
(Pins 10, 11 and 12) for input and output of serial data.
SDI (Pin 10): Serial Data Input. Data is clocked in on the
rising edge of the serial clock (SCK, Pin 11) when CS/LD
(Pin 9) is low.
SCK (Pin 11): Serial Clock.
SRO (Pin 12): Serial Readback Output. Data is clocked out
on the falling edge of SCK. Readback data begins clock
-
ing out after the first byte is clocked in. SRO is an active
output only when the chip is selected (i.e., when
CS
/LD is
low). Otherwise SRO presents a high-impedance output
in order to allow other parts to control the bus.
V
DD
(Pin 14): Positive Supply Input; 2.7V ≤ V
DD
≤ 5.5V.
Bypass with a 0.1μF low-ESR capacitor to ground.
CLR (Pin 17): Asynchronous Clear Input. When this pin
is low, all DAC registers (both code and span) are cleared
to zero. The DAC output is cleared to zero volts.
RFLAG (Pin 18): Reset Flag Output. An active low output
is asserted when there is a power-on reset or a clear event.
Returns high when an Update command is executed.
M-SPAN (Pin 19): Manual Span Control Pin. M-SPAN is
used in conjunction with pins S0, S1 and S2 (Pins 20, 21
and 22) to configure the DAC for operation in a single,
fixed output range.
To configure the part for manual-span use, tie M-SPAN
directly to V
DD
. The active output range is then set via
hardware pin strapping of pins S2, S1 and S0 (rather than
through the SPI port); and Write and Update commands
have no effect on the active output span.
To configure the part for SoftSpan use, tie M-SPAN directly
to GND. The output ranges are then individually control
-
lable through the SPI port; and pins S2, S1 and S0 have
no effect.
See Manual Span Configuration in the Operation section.
M-SPAN must be connected either directly to GND
(SoftSpan configuration) or to V
DD
(manual-span con-
figuration).
