LTC2756
17
2756fa
For more information www.linear.com/LTC2756
System Offset and Reference Adjustments
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2756, which is so low as to be
dominated by external output amplifier errors even when
using the most precise op amps.
The offset adjust pin V
OSADJ
can be used to null unipolar
offset or bipolar zero error. The offset change expressed
in LSB is the same for any output range:
∆V
OS
LSB
[ ]
=
OSADJ
V(R
)
• 2048
A 5V control voltage applied to V
OSADJ
produces ∆V
OS
=
–2048 LSB in any output range, assuming a 5V reference
voltage at R
IN
.
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
∆V
OS
= –(
1
/
128
)V
OSADJ
[0V to 5V, ±2.5V spans]
∆V
OS
= –(
1
/
64
)V
OSADJ
[0V to 10V, ±5V, –2.5V
to
7.5V spans]
∆V
OS
= –(
1
/
32
)V
OSADJ
[±10V span]
The gain error adjust pins GE
ADJ
can be used to null gain
error or to compensate for reference errors. The gain error
change expressed in LSB is the same for any output range:
∆GE =
ADJ
V(R
)
• 2048
The gain-error delta is non-inverting for positive reference
voltages.
Note that this pin compensates the gain by altering the
inverted reference voltage V(REF). In voltage terms, the
V(REF) delta is inverted and attenuated by a factor of 128.
∆V(REF) = –(
1
/
128
)GE
ADJ
The nominal input range of these pins is ±5V; other voltages
of up to ±15V may be used if needed. However, do not use
voltages divided down from power supplies; reference-
operaTion
quality, low-noise inputs are required to maintain the best
DAC performance.
The V
OSADJ
pin has an input impedance of 1.28MΩ. It
should be driven with a Thevenin-equivalent impedance
of 10k or less to preserve the settling performance of the
LTC2756. The V
OSADJ
pin should be shorted to GND if
not used.
The GE
ADJ
pin has an input impedance of 2.56MΩ, and
is intended for use with fixed reference voltages only. It
should be shorted to GND if not used.
Power-On Reset and Clear
When power is first applied to the LTC2756, the DAC
powers up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC output
initializes to zero volts.
If the part is configured for manual span operation, the
DAC will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC output is reset
to zero volts. The Input buffers are left intact, so that any
subsequent Update command (including the use of LDAC)
restores the DAC to its previous state.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply V
DD
dips below
approximately 2V; and stays asserted until any valid Update
command is executed.
