SI5110-H-BL Datasheet SI5110-H-BL, SI5110-H-GL, SI5110-F-BC | P25-P27

Si5110

Rev. 1.4 25

17. Pin Descriptions: Si5110

Number(s)

Name I/O Signal Level

Description

BWSEL1

BWSEL0

I LVTTL Transmit DSPLL Bandwidth Select.

The inputs select loop bandwidth of the Transmit

Clock Multiplier DSPLL as listed in Table 6.

Note: Both inputs have an internal pulldown.

H7 DLBK I LVTTL Diagnostic Loopback.

When this input is low, the transmit clock and data are

looped back for output on RXDOUT, RXCLK1 and

RXCLK2. This pin should be held high for normal

operation.

Note: This input has an internal pullup.

J5 FIFOERR O LVTTL FIFO Error.

This output is asserted (driven low) when a FIFO over-

flow/underflow has occurred. This output is low until

reset by asserting FIFORST.

H5 FIFORST

I LVTTL FIFO RESET.

When this input is low, the read/write FIFO pointers

are reset to their initial state.

Note: This input has an internal pullup.

B2, C2, D1,

E2, E7–9,

F2, F7–9,

G1, H2, J2,

GND GND

Supply Ground.

Connect to system GND. Ensure a very low

impedance path for optimal performance.

H8 LLBK

I LVTTL Line Loopback.

When this input is low, the recovered clock and data

are looped back for output on TXDOUT, and TXCLK-

OUT. Set this pin high for normal operation.

Note: This input has an internal pullup.

D2 LOS O LVTTL Loss-of-Signal.

This output is asserted (driven low) when the peak-to-

peak signal amplitude on RXDIN is below the thresh-

old set via LOSLVL.

B3 LOSLVL I

LOS Threshold Level.

Applying an analog voltage to this pin allows adjust-

ment of the Threshold used to declare LOS

. Tieing

this input to VREF disables LOS

detection and forces

the LOS

output high.

Si5110

26 Rev. 1.4

G8 LPTM I LVTTL Loop Timed Operation.

When this input is set low, the recovered clock from

the receiver is divided down and used as the refer-

ence source for the transmit CMU. The narrowband

setting for the DSPLL CMU is sufficient to provide

SONET compliant jitter generation and jitter transfer

on the transmit data and clock outputs (TXD-

OUT,TXCLKOUT). Set this pin high for normal opera-

tion.

Note: This input has an internal pullup.

C4 LTR I LVTTL Lock-to-Reference.

When the LTR input is set low, the receiver PLL will

lock to the selected reference clock. This function can

be used to force a stable output clock on the RXCLK1

and RXCLK2 outputs when no valid input data signal

is applied to RXDIN.

When the LTR

input is set high, the receiver PLL will

lock to the RXDIN signal (normal operation).

Note: This input has an internal pullup.

A2 PHASEADJ I Sampling Phase Adjust.

Applying an analog voltage to this pin allows adjust-

ment of the sampling phase across the data eye.

Tieing this input to VREF nominally centers the sam-

pling phase.

E10

F10

REFCLK+,

REFCLK–

I LVPECL

Differential Reference Clock.

This input is used as the Si5110 reference clock when

the REFSEL input is set high (REFSEL = 1). The ref-

erence clock sets the operating frequency of the

Si5110 transmit CMU, which is used to generate the

high-speed transmit clock TXCLKOUT. The reference

clock is also used by the Si5110 receiver CDR to cen-

ter the PLL during lock acquisition, and as a reference

for determination of the receiver lock status.

The REFCLK frequency is either 1/16th or 1/32nd of

the serial data rate (nominally 155 or 78 MHz,

respectively). The REFCLK frequency is selected

using the REFRATE input.

When REFSEL = 1, a valid reference clock must be

present.

Number(s)

Name I/O Signal Level

Description

Si5110

Rev. 1.4 27

F3 REFRATE I LVTTL Reference Clock Rate Select.

The REFRATE input sets the frequency for the

REFCLK input. When REFRATE is set high, the

REFCLK frequency is 1/16th the serial data rate

(nominally 155 MHz). When REFRATE is set low, the

REFCLK frequency is 1/32nd the serial data rate

(nominally 78 MHz).

The REFRATE input has no effect when the REFSEL

input is set low.

Note: This input has an internal pullup.

J7 REFSEL I LVTTL Reference Clock Selection.

This input selects the reference clock source to be

used by the Si5110 transmitter and receiver. The ref-

erence clock sets the operating frequency of the

Si5110 transmit CMU, which is used to generate the

high-speed transmit clock TXCLKOUT. The reference

clock is also used by the Si5110 receiver CDR to cen-

ter the PLL during lock acquisition, and as a reference

for determination of the receiver lock status.

When REFSEL = 0, the low-speed data input clock,

TXCLK4IN, is used as the reference clock. When

REFSEL = 1, the reference clock provided on

REFCLK is used.

Note: This input has an internal pullup.

E3 RESET I LVTTL Device Reset.

Forcing this input low for at least 1 μs causes a device

reset. For normal operation, this pin should be held

high.

Note: This input has an internal pullup.

A6, B6, C5,

G3, J3–4,

RSVD_GND

Reserved Tie To Ground.

Must be connected directly to GND for proper

operation.

B5 RXAMPMON O Analog

Receiver Amplitude Monitor.

The RXAMPMON output provides an analog output

signal that is proportional to the input signal

amplitude. See Equation 1 for the relationship

between RXAMPON and RXDIN. This signal is active

when SLICEMODE is asserted.

RXCLK1+,

RXCLK1–

OLVDS

Differential Receiver Clock Output 1.

The clock recovered from the signal present on

RXDIN is divided down to the parallel output word rate

and output on RXCLK1. In the absence of data, a sta-

ble clock on RXCLK1 can be maintained by asserting

LTR

Number(s)

Name I/O Signal Level

Description

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

SI5110-H-BL

Mfr. #:

Buy SI5110-H-BL

Manufacturer:

Silicon Labs

Description:

Clock Generators & Support Products OC-48/STM-16 SONET/SDH Transceiver

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SI5110-H-BL

SI5110-H-BL

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