LT1943
7
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GND (Pins 1, 20, Exposed Pad Pin 29): Ground. Tie both
GND pins and the exposed pad directly to a local ground
plane. The ground metal to the exposed pad should be as
wide as possible for better heat dissipation. Multiple vias
(to ground plane under the ground backplane) placed
close to the exposed pad can further aid in reducing
thermal resistance.
VC1 (Pin 2): Switching Regulator 1 Error Amplifier Com-
pensation. Connect a resistor/capacitor network in series
with this pin.
VC2 (Pin 3): Error Amplifier Compensation for Switcher 2.
Connect a resistor/capacitor network in series with this
pin.
FB1 (Pin 4): Switching Regulator 1 Feedback. Tie the
resistor divider tap to this pin and set V
LOGIC
according to
V
LOGIC
= 1.25 • (1 + R2/R1). Reference designators refer
to Figure 1.
FB2 (Pin 5): Feedback for Switch 2. Tie the resistor divider
tap to this pin and set AV
DD
according to AV
DD
= 1.25 •
(1 + R6/R5).
FB3 (Pin 6): Switching Regulator 3 Feedback. Tie the
resistor divider tap to this pin and set V
ON
according to
V
ON
= 1.25 • (1 + R9/R8) – 150mV.
NFB4 (Pin 7): Switching Regulator 4 Negative Feedback.
Switcher 4 can be used to generate a positive or negative
output. When regulating a negative output, tie the resistor
divider tap to this pin. Negative output voltage can be set
by the equation V
OFF
= –1.245 • (R3/R4) with R4 set to 10k.
Tie the NFB4 pin to FB4 for positive output voltages.
FB4 (Pin 8): Feedback for Switch 4. When generating a
positive voltage from switch 4, tie the resistor divider tap
to this pin. When generating a negative voltage, tie a 10k
resistor between FB4 and NFB4 (R4).
VC3 (Pin 9): Switching Regulator 3 Error Amplifier Com-
pensation. Connect a resistor/capacitor network in series
with this pin.
VC4 (Pin 10): Switching Regulator 4 Error Amplifier
Compensation. Connect a resistor/capacitor network in
series with this pin.
SGND (Pin 11): Signal Ground. Return ground trace from
the FB resistor networks and V
C
pin compensation compo-
nents directly to this pin and then tie to ground.
BOOST (Pin 12): The BOOST pin is used to provide a drive
voltage, higher than V
IN
, to the switch 1 drive circuit.
SW1 (Pins 13, 14): The SW1 pins are the emitter of the
internal NPN bipolar power transistor for switching regu-
lator 1. These pins must be tied together for proper
operation. Connect these pins to the inductor, catch diode
and boost capacitor.
V
IN
(Pins 15, 16): The V
IN
pins supply current to the
LT1943’s internal regulator and to the internal power
transistor for switch 1. These pins must be tied together
and locally bypassed.
SS-234 (Pin 17): This is the soft-start pin for switching
regulators 2, 3 and 4. Place a soft-start capacitor here to
limit start-up inrush current and output voltage ramp rate.
When the BIAS pin reaches 2.8V, a 1.7µA current source
begins charging the capacitor. When the capacitor voltage
reaches 0.8V, switches 2, 3 and 4 turn on and begin
switching. For slower start-up, use a larger capacitor.
When this pin is pulled to ground, switches 2, 3 and 4 are
disabled. For complete shutdown, tie RUN-SS to ground.
RUN-SS (Pin 18): This is the soft-start pin for switching
regulator 1. Place a soft-start capacitor here to limit start-
up inrush current and output voltage ramp rate. When
power is applied to the V
IN
pin, a 1.7µA current source
charges the capacitor. When the voltage at this pin reaches
0.8V, switch 1 turns on and begins switching. For slower
start-up, use a larger capacitor. For complete shutdown,
tie RUN-SS to ground.
SW4 (Pin 19): This is the collector of the internal NPN
bipolar power transistor for switching regulator 4. Mini-
mize metal trace area at this pin to keep EMI down.
UU
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LT1943
8
1943fa
SW3 (Pin 21): This is the collector of the internal NPN
bipolar power transistor for switching regulator 3. Mini-
mize metal trace area at this pin to keep EMI down.
BIAS (Pin 22): The BIAS pin is used to improve efficiency
when operating at higher input voltages. Connecting this
pin to the output of switching regulator 1 forces most of
the internal circuitry to draw its operating current from
V
LOGIC
rather than V
IN
. The drivers of switches 2, 3 and 4
are supplied by BIAS. Switches 2, 3 and 4 will not switch
until the BIAS pin reaches approximately 2.8V. BIAS must
be tied to V
LOGIC
.
PGOOD (Pin 23): Power Good Comparator Output. This is
the open collector output of the power good comparator
and can be used in conjunction with an external P-Channel
MOSFET to provide output disconnect for AV
DD
as shown
in the 5V Input, Quad Output TFT-LCD Power Supply on
the last page of the data sheet. When switcher 2’s output
reaches approximately 90% of its programmed voltage,
PGOOD will be pulled to ground. This will pull down on the
gate of the MOSFET, connecting AV
DD
. A 100k pull-up
resistor between the source and gate of the P-channel
MOSFET keeps it off when switcher 2’s output is low.
E3 (Pin 24): This is switching regulator 3’s output and the
emitter of the output disconnect PNP. Tie the output
capacitor and resistor divider here.
C
T
(Pin 25): Timing Capacitor Pin. This is the input to the
V
ON
timer and programs the time delay from all four
feedback pins reaching 1.125V to V
ON
turning on. The C
T
capacitor value can be set using the equation C = (20µA •
t
DELAY
)/1.1V.
V
ON
(Pin 26): This is the delayed output for switching
regulator 3. V
ON
reaches its programmed voltage after the
internal C
T
timer times out. Protection circuitry ensures
V
ON
is disabled if any of the four outputs are more than
10% below normal voltage.
SW2 (Pins 27, 28): The SW2 pins are the collector of the
internal NPN bipolar power transistor for switching regu-
lator 2. These pins must be tied together. Minimize trace
area at these pins to keep EMI down.
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LT1943
9
1943fa
BLOCK DIAGRA
W
Figure 1. Block Diagram
+
+
SQ
R
DRIVER
400mA
SWITCH
Σ
SLOPE
COMPENSATION
FOLDBACK
OSCILLATOR
21
6
1
9
+
+
+
SQ
R
DRIVER
400mA
SWITCH
Σ
SLOPE
COMPENSATION
FOLDBACK
OSCILLATOR
19
17
10
+
+
+
SQ
R
DRIVER
2.6A
SWITCH
Σ
SLOPE
COMPENSATION
FOLDBACK
OSCILLATOR
27
28
22
25
5
23
15
26
3
+
+
SQ
R
DRIVER
2.4A
SWITCH
Σ
SLOPE
COMPENSATION
FOLDBACK
OSCILLATOR
2
12
4
gm
gm
gm
gm
1.25V
1.25V
FB3
GND
11
SGND
20
GND
29
GND
SS-234
RUN-SS
R8
R9
MASTER
OSCILLATOR
1.2MHz
+
V
C4
V
C3
SW3
E3
V
E3
V
C2
V
C1
BIAS
SW2
8
FB4
7
NFB4
SW4
V
ON
V
ON
V
E3
1.1V
1.125V
+
1.12V
1.25V
1.25V
C
T
FB2
FB1
V
LOGIC
PGOOD
20µA
16
V
IN
V
IN
BOOST
INTERNAL
REGULATOR
AND
REFERENCE
SW2
SW3
SW4
LOCKOUT
1.7µA
1.7µA
BIAS
2.8V
V
IN
18
C4
C15
C10
C22
C7
C6
C13
C5
24
R3
R4
R12
C23
C14
C24
R13
C21
C12
R11
C20
C11
R10
L5
V
IN
V
LOGIC
V
LOGIC
V
OFF
C16
C8
C1
C9
V
IN
AV
DD
C2
L1
C3
D2
D1
L2
14
13
SW1
D3
D6
D5
L4
L3
R5
R6
R14
R1
R2
AV
DD
+

LT1943EFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi C 4x Out Reg for TFT LCD Panels
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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