MC88915
LOW SKEW CMOS PLL CLOCK DRIVERS
IDT™ / ICS™
CMOS PLL CLOCK DRIVERS 7
MC88915 REV 6 JULY 10, 2007
Figure 4. Depiction of the Fixed SYNC to Feedback Offset (t
PD
)
Which is Present When a 470 kΩ Resistor is Tied to V
CC
or Ground
5. The t
SKEWr
specification guarantees the rising edges of
outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall
within a 500 ps window within one part. However, if the
relative position of each output within this window is not
specified, the 500 ps window must be added to each
side of the t
PD
specification limits to calculate the total
part-to-part skew. For this reason, the absolute
distribution of these outputs are provided in Table 9.
When taking the skew data, Q0 was used as a
reference, so all measurements are relative to this
output. The information in Ta b l e 9 is derived from
measurements taken from the 14 process lots described
in Note 1, over the temperature and voltage range.
6. Calculation of Total Output-to-Skew Between
Multiple Parts (Part-to-Part Skew)
By combining the t
PD
specification and the information in
Note 5, the worst case output-to-output skew between
multiple 88915s connected in parallel can be calculated.
This calculation assumes all parts have a common
SYNC input clock with equal delay of input signal to each
part. This skew value is valid at the 88915 output pins
only (equally loaded), it does not include PCB trace de-
lays due to varying loads.
With a 1.0 MΩ resistor tied to analog V
CC
as shown in
Note 4, the t
PD
spec. limits between SYNC and the Q/2
output (connected to the FEEDBACK pin) are –1.05 ns
and –0.5 ns. To calculate the skew of any given output
between two or more parts, the absolute value of the dis-
tribution of the output given in Tab le 9 must be subtract-
ed and added to the lower and upper t
PD
spec limits
respectively. For output Q2, [276 – (–44)] = 320 ps is the
absolute value of the distribution. Therefore, [–1.05 ns –
0.32 ns] = –1.37 ns is the lower t
PD
limit, and [–0.5 ns +
0.32 ns] = –0.18 ns is the upper limit. Therefore, the
worst case skew of output Q2 between any number of
parts is |(–1.37) – (–0.18)| = 1.19 ns. Q2 has the worst
case skew distribution of any output, so 1.2 ns is the ab-
solute worst case output-to-output skew between multi-
ple parts.
7. Note 4 explains that the t
PD
specification was measured
and is guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10 MHz. The fixed offset (t
PD
) as described
above has some dependence on the input frequency
and at what frequency the VCO is running. The graphs
of Figure 5 demonstrate this dependence.
The data presented in Figure 5 is from devices repre-
senting process extremes, and the measurements were
also taken at the voltage extremes (V
CC
= 5.25 V and
4.75 V). Therefore, the data in Figure 5 is a realistic rep-
resentation of the variation of t
PD
.
EXTERNAL LOOP FILTER
330 Ω
0.1 µF
RC1
R2
C1
ANALOG GND
With the 470 kΩ resistor tied in this fashion, the t
PD
specification measured at the input pins is:
t
PD
= –0.775 ns ± 0.275 ns
ANALOG V
CC
330 Ω
0.1 µF
R2
C1
ANALOG GND
RC1
SYNC INPUT
FEEDBACK OUTPUT
2.25 ns OFFSET
3.0 V
5.0 V
SYNC INPUT
FEEDBACK OUTPUT
–0.775 ns OFFSET
3.0 V
5.0 V
With the 470 kΩ resistor tied in this fashion, the t
PD
specification measured at the input pins is:
t
PD
= 2.25 ns ± 1.0 ns
1 MΩ
or
470 kΩ
Reference
Resistor
1 MΩ
or
470 kΩ
Reference
Resistor
Table 9. Relative Positions of Outputs Q/2, Q0–Q4,
2X_Q Within the 500 ps t
SKEWr
Spec Window
Output – (ps) + (ps)
Q0 0 0
Q1 –72 40
Q2 –44 276
Q3 –40 255
Q4 –274 –34
Q/2 –16 250
2X_Q –633 –35
