LTC1164-6CSW#TRPBF

7
LTC1164-6
11646fa
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(14-Lead Dual-In-Line Package)
buffer, Figure 3,can be used provided that its input common
mode range is well within the filter’s output swing. Pin 6 is
an intermediate filter output providing an unspecified 6th
order lowpass filter. Pin 6 should not be loaded.
ELLIPTIC/LINEAR PHASE (Pin 10): The DC level at this pin
selects the desired filter response, elliptic or linear phase
and determines the ratio of the clock frequency to the
cutoff frequency of the filter. Pin 10 connected to V
provides an elliptic lowpass filter with clock-to-f
CUTOFF
ratio of 100:1. Pin 10 connected to analog ground pro-
vides a linear phase lowpass filter with a clock- to-f
–3dB
ratio of 160:1 and a transient response overshoot of 1%.
When Pin 10 is connected to V
+
the clock-to-f
CUTOFF
ratio
is 50:1 and the filter response is elliptic. Bypassing Pin 10
to analog ground reduces the output DC offsets. If the DC
level at Pin 10 is switched mechanically or electrically at
slew rates greater than 1V/µs while the device is operating,
a 10k resistor should be connected between Pin 10 and the
DC source.
CLK (Pin 11): Any TTL or CMOS clock source with a
square-wave output and 50% duty cycle (±10%) is an
adequate clock source for the device. The power supply for
the clock source should not be the filter’s power supply.
The analog ground for the filter should be connected to
clock’s ground at a single point only. Table 1 shows the
clock’s low and high level threshold value for a dual or
single supply operation. A pulse generator can be used as
a clock source provided the high level ON time is greater
than 0.5µs. Sine waves are not recommended for clock
input frequencies less than 100kHz, since excessively
slow clock rise or fall times generate internal clock jitter
(maximum clock rise or fall time 1µs). The clock signal
should be routed from the right side of the IC package to
avoid coupling into any input or output analog signal path.
A 1k resistor between clock source and Pin 11 will slow
down the rise and fall times of the clock to further reduce
charge coupling, Figures 1 and 2.
1k
1164-6 F03
+
LT1006, f
C
< 5kHz
LT1200, f
C
> 5kHz
Figure 3. Buffer for Filter Output
V
(Pins 7, 14): Pins 7 and 14 should be connected
together. In a printed circuit board the connection should
be done under the IC package through a short trace
surrounded by the analog ground plane.
V
OUT
(Pins 9, 6): Pin 9 is the specified output of the filter;
it can typically source or sink 1mA. Driving coaxial cables
or resistive loads less than 20k will degrade the total
harmonic distortion of the filter. When evaluating the device’s
distortion an output buffer is required. A noninverting
could go above ground, a signal diode must be used to
clamp V. Figures 1 and 2 show typical connections for dual
and single supply operation.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
IN
V
+
1k
V
V
OUT
LTC1164-6
DIGITAL SUPPLY
+
GND
CLOCK SOURCE
*
1164-6 F01
* OPTIONAL
0.1µF
0.1µF
Figure 1. Dual Supply Operation for f
CLK
/f
CUTOFF
= 100:1
Table 1. Clock Source High and Low Threshold Levels
POWER SUPPLY HIGH LEVEL LOW LEVEL
Dual Supply = ±7.5V 2.18V 0.5V
Dual Supply = ±5V 1.45V 0.5V
Dual Supply = ±2.5V 0.73V 2.0V
Single Supply = 12V 7.80V 6.5V
Single Supply = 5V 1.45V 0.5V
Figure 2. Single Supply Operation for f
CLK
/f
CUTOFF
= 100:1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
IN
V
+
1k
V
OUT
DIGITAL SUPPLY
+
GND
CLOCK SOURCE
1164-6 F02
+
LTC1164-6
0.1µF
1µF
10k
10k
8
LTC1164-6
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Passband Response
The passband response of the LTC1164-6 is optimized for
a f
CLK
/f
CUTOFF
ratio of 100:1. Minimum passband ripple
occurs from 1Hz to 80% of f
CUTOFF
. Athough the passband
of the LTC1164-6 is optimized for ratio f
CLK
/f
CUTOFF
of
100:1, if a ratio of 50:1 is desired, connect a single pole
lowpass RC (f
–3dB
= 2 f
CUTOFF
) at the output of the filter.
The RC will make the passband gain response as flat as the
100:1 case. If the RC is omitted, and clock frequencies are
below 500kHz the passband gain will peak by 0.4dB at
90% f
CUTOFF
.
Table 2. Typical Passband Ripple with Single 5V Supply
(f
CLK
/f
C
)
= 100:1, GND = 2V, 30kHz, Fixed Single Pole, Lowpass
RC Filter at Pin 9 (See Typical Applications)
PASSBAND PASSBAND GAIN
FREQUENCY (REFERENCED TO 0dB)
f
CUTOFF
= 1kHz f
CUTOFF
= 10kHz
T
A
= 25°CT
A
= 0°CT
A
= 25°CT
A
= 70°C
% of f
CUTOFF
(dB) (dB) (dB) (dB)
10 0.00 0.00 0.00 0.00
20 0.02 0.00 0.01 0.01
30 0.05 0.01 0.01 0.01
40 0.10 0.02 0.02 0.02
50 0.13 0.03 0.01 0.03
60 0.15 0.01 0.01 0.05
70 0.18 0.01 0.01 0.07
80 0.25 0.08 0.05 0.02
90 0.39 0.23 0.18 0.05
f
CUTOFF
2.68 2.79 2.74 2.68
The gain peaking can approximate a sin χ/χ correction for
some applications. (See Typical Performance Characteristics
curve, Passband vs Frequency and f
CLK
at f
CLK
/f
C
= 50:1.)
When the LTC1164-6 operates with a single 5V supply and its
cutoff frequency is clock-tuned to 10kHz, an output single
pole RC filter can also help maintain outstanding passband
flatness from 0°C to 70°C. Table 2 shows details.
Clock Feedthrough
Clock feedthrough is defined as, the RMS value of the
clock frequency and its harmonics that are present at the
filter’s output (Pin 9). The clock feedthrough is tested with
the input (Pin 2) grounded and, it depends on PC board
layout and on the value of the power supplies. With proper
layout techniques the values of the clock feedthrough are
shown in Table 3.
Table 3. Clock Feedthrough
V
S
50:1 100:1
±2.5V 60µV
RMS
60µV
RMS
±5V 100µV
RMS
200µV
RMS
±7.5V 150µV
RMS
500µV
RMS
Note: The clock feedthrough at ±2.5V supplies is imbedded in the wideband noise of the filter. (The
clock signal is a square wave.)
Any parasitic switching transients during the rise and fall
edges of the incoming clock are not part of the clock
feedthrough specifications. Switching transients have fre-
quency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, if bothersome, can be greatly reduced
by adding a simple R/C lowpass network at the output of
the filter (Pin 9). This R/C will completely eliminate any
switching transient.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and it is used to
determine the operating signal-to-noise ratio. Most of its
frequency contents lie within the filter passband and it
cannot be reduced with post filtering. For instance, the
LTC1164-6 wideband noise at ±2.5V supply is 100µV
RMS
,
90µV
RMS
of which have frequency contents from DC up to
the filter’s cutoff frequency. The total wideband noise
(µV
RMS
) is nearly independent of the value of the clock.
The clock feedthrough specifications are not part of the
wideband noise.
Speed Limitations
The LTC1164-6 optimizes AC performance versus power
consumption. To avoid op amp slew rate limiting at
maximum clock frequencies, the signal amplitude should
be kept below a specified level as shown on Table 4.
Aliasing
Aliasing is an inherent phenomenon of sampled data
systems and it occurs when input frequencies close to the
sampling frequency are applied. For the LTC1164-6 case,
an input signal whose frequency is in the range of f
CLK
±4%, will be aliased back into the filter’s passband. If, for
instance, an LTC1164-6 operating with a 100kHz clock
9
LTC1164-6
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and 1kHz cutoff frequency receives a 98.5kHz, 10mV
RMS
input signal, a 1.5kHz, 10µV
RMS
alias signal will appear at
its output. When the LTC1164-6 operates with a clock-to-
cutoff frequency of 50:1, aliasing occurs at twice the clock
frequency. Table 5 shows details.
Table 4. Maximum V
IN
vs V
S
and f
CLK
POWER SUPPLY MAXIMUM f
CLK
MAXIMUM V
IN
±7.5V 1.5MHz 1V
RMS
(f
IN
> 35kHz)
1MHz 3V
RMS
(f
IN
> 25kHz)
1MHz 0.7V
RMS
(f
IN
> 250kHz)
±5V 1MHz 2.5V
RMS
(f
IN
> 25kHz)
1MHz 0.5V
RMS
(f
IN
> 100kHz)
Single 5V 1MHz 0.7V
RMS
(f
IN
> 25kHz)
1MHz 0.5V
RMS
(f
IN
> 100kHz)
Table 5. Aliasing (f
CLK
= 100kHz)
INPUT FREQUENCY OUTPUT LEVEL OUTPUT FREQUENCY
(V
IN
= 1V
RMS
) (Relative to Input) (Aliased Frequency)
(kHz) (dB) (kHz)
f
CLK
/f
C
= 100:1, f
CUTOFF
= 1kHz
96 (or 104) 75.0 4.0
97 (or 103) 68.0 3.0
98 (or 102) 65.0 2.0
98.5 (or 101.5) 60.0 1.5
99 (or 101) 3.2 1.0
99.5 (or 100.5) 0.5 0.5
f
CLK
/f
C
= 50:1, f
CUTOFF
= 2kHz
192 (or 208) 76.0 8.0
194 (or 206) 68.0 6.0
196 (or 204) 63.0 4.0
198 (or 202) 3.4 2.0
199 (or 201) 1.3 1.0
199.5(or 200.5) 0.9 0.5
Table 6. Transient Response of LTC Lowpass Filters
DELAY RISE SETTLING OVER-
TIME* TIME** TIME*** SHOOT
LOWPASS FILTER (SEC) (SEC) (SEC) (%)
LTC1064-3 Bessel 0.50/f
C
0.34/f
C
0.80/f
C
0.5
LTC1164-5 Linear Phase 0.43/f
C
0.34/f
C
0.85/f
C
0
LTC1164-6 Linear Phase 0.43/f
C
0.34/f
C
1.15/f
C
1
LTC1264-7 Linear Phase 1.15/f
C
0.36/f
C
2.05/f
C
5
LTC1164-7 Linear Phase 1.20/f
C
0.39/f
C
2.20/f
C
5
LTC1064-7 Linear Phase 1.20/f
C
0.39/f
C
2.20/f
C
5
LTC1164-5 Butterworth 0.80/f
C
0.48/f
C
2.40/f
C
11
LTC1164-6 Elliptic 0.85/f
C
0.54/f
C
4.30/f
C
18
LTC1064-4 Elliptic 0.90/f
C
0.54/f
C
4.50/f
C
20
LTC1064-1 Elliptic 0.85/f
C
0.54/f
C
6.50/f
C
20
* To 50% ±5%, ** 10% to 90% ±5%, *** To 1% ±0.5%
8th Order Elliptic Lowpass Filter
(f
CLK
/f
C
) = 50:1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LTC1164-6
V
IN
V
OUT
f
CLK
V
+
NOTES:
1. OPTIONAL OUTPUT BUFFER
1/2πRC = (2)(f
CUTOFF
)
2. PINS 1, 8, 13 CAN BE GROUNDED
OR LEFT FLOATING
1164-6 TA06
C
+
V
0.1µF
R
V
+
V
LT
®
1006
0.1µF
V
+
INPUT
90%
50%
10%
OUTPUT
t
r
t
d
t
s
1164-6 F04
RISE TIME (t
r
) = ±5%
0.54
f
CUTOFF
SETTLING TIME (t
s
) = ±5%
(TO 1% of OUTPUT)
4.3
f
CUTOFF
TIME DELAY (t
d
) = GROUP DELAY
(TO 50% OF OUTPUT)
0.85
f
CUTOFF
Figure 4
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LTC1164-6CSW#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Active Filter L/P Clk Sweepable Cauer Filter
Lifecycle:
New from this manufacturer.
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