LTC4306IUFD#PBF Datasheet LTC4306IUFD#PBF, LTC4306CGN#PBF, LTC4306IGN#PBF | P10-P12

LTC4306

4306f

The LTC4306 is a 4-channel, 2-wire bus multiplexer/

switch with bus buffers to provide capacitive isolation

between the upstream bus and downstream buses. Mas-

ters on the upstream 2-wire bus (SDAIN and SCLIN) can

command the LTC4306 to any combination of the 4

downstream buses. Masters can also program the LTC4306

to disconnect the upstream bus from the downstream

buses if the bus is stuck low.

Undervoltage Lockout (UVLO) and ENABLE

Functionality

The LTC4306 contains undervoltage lockout circuitry that

maintains all of its SDA, SCL, GPIO and ALERT pins in high

impedance states until the device has sufficient V

supply

voltage to function properly. It also ignores any attempts

to communicate with it via the 2-wire buses in this condi-

tion. When the ENABLE pin voltage is low (below 0.8V), all

control bits are reset to their default high impedance

states, and the LTC4306 ignores 2-wire bus commands.

However, with ENABLE low, the LTC4306 still monitors

the ALERT1-ALERT4 pin voltages and pulls the ALERT pin

low if any of ALERT1-ALERT4 is low. When ENABLE is

high, devices can read from and write to the LTC4306.

Connection Circuitry

Masters on the upstream SDAIN/SCLIN bus can write to

the Bus 1 FET State through Bus 4 FET State bits of register

3 to connect to any combination of downstream channels

1 to 4. By default, the Connection Circuitry shown in the

Block Diagram will only connect to downstream channels

whose corresponding Bus Logic State bits in register 3 are

high at the moment that it receives the connection com-

mand. If the LTC4306 is commanded to connect to mul-

tiple channels at once, it will only connect to the channels

that are high. Masters can override this feature by setting

the Connection Requirement bit of register 2 high. With

this bit high, the LTC4306 executes connection com-

mands without regard to the logic states of the down-

stream channels.

Upon receiving the connection command, the Connec-

tion Circuitry will activate the Upstream-Downstream

Buffers under two conditions: first, the master must be

commanding connection to one or more downstream

channels, and second, there must be no stuck low

condition (see Stuck Low Timeout Fault discussion). If

the connection command is successful, the Upstream-

Downstream Buffers pass signals between the upstream

bus and the connected downstream buses. The LTC4306

also turns off its N-channel MOSFET open-drain pull-

down on the READY pin, so that READY can be pulled

high by its external pull-up resistor.

Upstream-Downstream Buffers

Once the Upstream-Downstream Buffers are activated,

the functionality of the SDAIN and any connected down-

stream SDA pins is identical. A low forced on any con-

nected SDA pin at any time results in all pins being low.

External devices must pull the pin voltages below 0.4V

worst-case with respect to the LTC4306’s ground pin to

ensure proper operation. The SDA pins enter a logic high

state only when all devices on all connected SDA pins force

a high. The same is true for SCLIN and the connected

downstream SCL pins. This important feature ensures

that clock stretching, clock arbitration and the acknowl-

edge protocol always work, regardless of how the devices

in the system are connected to the LTC4306.

The Upstream-Downstream Buffers provide capacitive

isolation between SDAIN/SCLIN and the downstream con-

nected buses. Note that there is no capacitive isolation

between connected downstream buses; they are only

separated by the series combination of their switches’ on

resistances.

While any combination of downstream buses may be

connected at the same time, logic high levels are corrupted

if multiple downstream buses are active and both the V

voltage and one or more downstream bus pull-up voltages

are larger than the pull-up supply voltage for another

downsteam bus. An example of this issue is shown in

Figure 1. During logic highs, DC current flows from V

BUS1

through the series combination of R1, N1, N2 and R2 and

into V

BUS2

, causing the SDA1 voltage to drop and current

to be sourced into V

BUS2

. To avoid this problem, do not

activate bus 1 or any other downstream bus whose pull-

up voltage is above 2.5V when bus 2 is active.

OPERATIO

LTC4306

4306f

Rise Time Accelerators

The Upstream Accelerators Enable and Downstream Ac-

celerators Enable bits of register 1 activate the upstream

and downstream rise time accelerators, respectively.

When activated, the accelerators turn on in a controlled

manner and source current into the pins during positive

bus transitions.

When no downstream buses are connected, an upstream

accelerator turns on when its pin voltage exceeds 0.8V

and is rising at a minimum slew rate of 0.8V/µs. When one

or more downstream buses are connected, the accelera-

tor on a given pin turns on when these conditions are met:

first, the pin’s voltage is rising at a minimum slew rate of

0.8V/µs; second, the voltages on both the upstream bus

and the connected downstream buses exceed 0.8V.

Note that a downstream bus’s switch must be closed in

order for its rise time accelerator current to be active. See

the Applications Section for choosing a bus pull-up resis-

tor value to ensure that the rise time accelerator switches

turn on. Do not activate boost currents on a bus whose

pull-up supply voltage V

BUS

is less than V

. Doing so

would cause the boost currents to source current from

into the V

BUS

supply during rising edges.

Downstream Bus Connection Fault

By default, the LTC4306 will only connect to downstream

channels whose SDA and SCL pins are both high (above

1V) at the moment that it receives the connection com-

mand. In this case, the LTC4306 sets the Failed Connec-

tion Attempt bit of register 0 low and pulls the ALERT pin

low when the master tries to connect to a low downstream

channel. Note that users can write a high to the Connection

Requirement bit of register 2 high to program the LTC4306

to connect to downstream channels regardless of their

logic state at the moment of connection. In this case, the

downstream channel connection fault never occurs.

Stuck Low Timeout Fault

The stuck low timeout circuitry monitors the two common

internal nodes of the downstream SDA and SCL switches

and runs a timer whenever either of the internal node

voltages is below 0.52V. The timer is reset whenever both

internal node voltages are above 0.6V. If the timer ever

reaches the time programmed by Timeout Mode Bits 1 and

0 of register 2, the LTC4306 pulls ALERT low and discon-

nects the downstream bus(es) from the upstream bus by

de-biasing the Upstream-Downstream Buffers. Note that

the downstream switches remain in their existing state.

The Timeout Real-Time bit of register 0 indicates the real-

time status of the stuck low situation. The Latched Timeout

Bit of register 0 is a latched bit that is set high when a

timeout occurs.

External Faults on the Downstream Channels

When a slave on downstream bus 1 pulls the ALERT1 pin

below 1V, the LTC4306 passes this information to the

master on the upstream bus by pulling the ALERT pin low.

The same is true for the other three downstream buses.

Each bus has its own dedicated fault bit in Register 0, so

that masters can read Register 0 to determine which buses

have faults.

ALERT Functionality and Fault Resolution

When a fault occurs, the LTC4306 pulls the ALERT pin low,

as described previously. The procedure for resolving

faults depends on the type of fault. If a master on the

upstream bus is communicating with devices on a down-

stream bus via the Upstream-Downstream Buffer cir-

cuitry—channel 1, for example—and a device on this bus

pulls the ALERT1 pin low, the LTC4306 acts transparently,

and the master communicates directly with the device that

caused the fault via the upstream-downstream buffer

circuitry to resolve the fault.

OPERATIO

SDA1

4306 F01

SDA2

= V

BUS1

= 5V

BUS2

= 2.5V

10k

Figure 1. Example of Unacceptable Level Shifting

LTC4306

4306f

In all other cases, the LTC4306 communicates with the

master to resolve the fault. After the master broadcasts the

Alert Response Address (ARA), the LTC4306 will respond

with its address on the SDAIN line and release the ALERT

pin. The ALERT line will also be released if the LTC4306 is

addressed by the master.

The ALERT signal will not be pulled low again until a

different type of fault has occurred or the original fault is

cleared and it occurs again. Figure 2 shows the details of

how the ALERT pin is set and reset. The downstream bus

connection fault and faults that occur on unconnected

downstream buses are grouped together and generate a

single signal to drive ALERT. The stuck low timeout fault

has its own dedicated pathway to ALERT; however, once

a stuck low occurs, another one will not occur until the first

one is cleared. For these reasons, once the master has

established the LTC4306 as the source of the fault, it

should read register 0 to determine the specific problem,

take action to solve the problem, and clear the fault

promptly. All faults are cleared by writing a dummy data

byte to register 0, which is a read-only register.

For example, assume that a fault occurs, the master sends

out the ARA, and the LTC4306 successfully writes

its address onto SDAIN and releases its ALERT pin. The

master reads register 0 and learns that the ALERT2 logic

state bit is low. The master now knows that a device on

downstream bus 2 has a fault and writes to register 3 to

connect to bus 2, so that it can communicate with the

source of the fault. At this point, the master writes to

C Device Addressing

Twenty-seven distinct bus addresses are configurable

using the three state ADR0, ADR1 and ADR2 pins. Table 1

shows the correspondence between pin states and ad-

dresses. Note that address bits a6 and a5 are internally

configured to 1 and 0 respectively. In addition, the LTC4306

responds to two special addresses. Address (1011 101) is

a mass write used to write all LTC4306’s, regardless of

their individual address settings. The mass write can be

masked by setting the Mass Write Enable bit of register 2

to zero. Address (0001 100) is the SMBus Alert Response

Address. Figure 3 shows data transfer over a 2-wire bus.

Supported Commands

Users must write to the LTC4306 using the SMBus Write

Byte protocol and read from it using the Read Byte

protocol. During fault resolution, the LTC4306 also

supports the Alert Response Address protocol. The

formats for these protocols are shown in Figure 4. Users

must follow the Write Byte protocol exactly to write to the

LTC4306; if a Repeated Start Condition is issued before a

Stop Condition, the LTC4306 ignores the attempted write,

and its control bits remain in their preexisting state. When

OPERATIO

4306 F02

WRITE

FAULT ON CONNECTED

DOWNSTREAM BUS

WRITE

FAULT ON DISCONNECTED

DOWNSTREAM BUS

CONNECTION FAULT

ADDRESS LTC4306

STUCK BUS

LTC4306 RESPONDS

TO ARA

ALERT

Figure 2. Setting and Resetting the ALERT Pin

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LTC4306IUFD#PBF

Mfr. #:

Buy LTC4306IUFD#PBF

Manufacturer:

Analog Devices Inc.

Description:

Multiplexer Switch ICs 4:1 I2C MUX and Bus Buffer

Lifecycle:

New from this manufacturer.

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LTC4306IUFD#PBF

LTC4306IUFD#PBF

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