Evaluates: MAX9235/MAX9206
MAX9235 Evaluation Kit
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Quick Start
Recommended Equipment
Before beginning, the following equipment is needed:
• 3.3V DC power supply
• Two clock generators
• Data generator for LVCMOS/LVTTL 10-bit parallel
signal input
• Logic analyzer or data-acquisition system or oscillo-
scope
Procedure
The MAX9235 EV kit is fully assembled and tested.
Follow the steps below to verify board operation.
Caution: Do not turn on the power supply or enable
the clock generators until all connections are
completed.
1) Verify that all shunts are in their default positions.
See Table 1 for default shunt positions.
2) Connect the 3.3V power supply to the +3.3V pad.
Connect the ground terminal of this supply to the
GND pad.
3) Connect the data generator to 24-pin connector J1
and set it to generate 10-bit parallel data at
LVCMOS/LVTTL levels (high-level input from 2V to
VCC and low-level input from 0.8V to GND). See
Table 2 for input bit locations.
4) Connect the first clock generator to SMA connector
J2 and set it for an output with a frequency of
16MHz to 40MHz. Use LVCMOS/LVTTL levels. Note
that the TCLK SMA connector is terminated with
two parallel-connected 100Ω resistors.
5) Connect the second clock generator to SMA con-
nector J3 and set it for the same frequency as the
first clock generator. The frequency tolerance
between the two clocks should not be larger than
1%. Note that the REFCLK SMA connector is termi-
nated with two parallel-connected 100Ω resistors.
6) Set the logic analyzer or data-acquisition system for
LVCMOS/LVTTL level signal input.
7) Connect the logic analyzer or data-acquisition sys-
tem or oscilloscope to the signal output 24-pin con-
nector J4. See Table 2 for output bit locations.
8) Turn on the power supply.
9) Enable the first clock generator.
10) Enable the second clock generator.
11) Enable the data generator.
12) Enable the logic analyzer or data-acquisition sys-
tem and begin sampling data.
Detailed Description
The MAX9235 EV kit is a fully assembled and tested
PCB that simplifies the evaluation of the MAX9235
400Mbps, 10-bit LVDS serializer and the MAX9206
400Mbps, 10-bit LVDS deserializer.
The serializer/deserializer data transfer starts with the
serializer initially locking onto the reference clock and
then sending the serialized data to the deserializer.
A start-bit high and a stop-bit low frame the 10-bit data
and function as the embedded clock edge in the serial
data stream. The serial rate is the TCLK frequency
times the data and appended bits. For example, if
TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) =
480Mbps. Since only 10 bits are from input data, the
payload rate is 40 x 10 = 400Mbps.
The serializer output pins (OUT+ and OUT-) are held in
high impedance when V
CC
is first applied and while the
PLL is locking to the local reference clock. If the serial-
izer goes into high impedance, the deserializer loses
PLL lock and needs to reestablish phase lock before
data transfer can resume. This is done by transmitting
all zeros for at least one frame.
The EV kit requires a single 3.3V supply to operate and
two reference clock inputs in the 16MHz to 40MHz
range. The 10-bit parallel input data can be supplied to
24-pin header J1 with a data generator running at the
same frequency as the reference clock, or the bits can
be configured by manually installing shunts across
header J1 pins. The output 10-bit parallel data can be
sampled or individually tested at 24-pin header J4.
The first reference clock is for the serializer PLL reference.
The second reference clock is for the deserializer PLL ref-
erence. The tolerance between the two references should
not be larger than 1%. They can share a clock signal by a
splitter. In real applications, the serializer and deserializer
references may connect to a single system clock.
Input Signal
The MAX9235 EV kit accepts 10-bit parallel data at
LVCMOS/LVTTL levels (high-level input from 2V to V
CC
and low-level input from 0.8V to GND). The 10-bit pat-
tern can be supplied to the EV kit by connecting a data
generator to 24-pin header J1 or by connecting select-
ed J1 pins to a high/low LVCMOS/LVTTL state. See
Table 2 for input bit locations on 24-pin header J1.
Output Signal
The MAX9235 EV kit outputs 10-bit parallel data at
LVCMOS/LVTTL levels on 24-pin header J4. To sample
the 10-bit pattern, connect a logic analyzer or data-
acquisition system to J4. See Table 2 for the output bit
locations on 24-pin header J4.
