3
AT28C64B
0270I–PEEPR–08/03
Device Operation READ: The AT28C64B is accessed like a Static RAM. When CE and OE are low and
WE
is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high-impedance state when either
CE
or OE is high. This dual line control gives designers flexibility in preventing bus con-
tention in their systems.
BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and
OE
high initiates a write cycle. The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising edge of CE
or WE. Once a
byte write has been started, it will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the duration of t
WC
, a read operation will
effectively be a polling operation.
PAGE WRITE: The page write operation of the AT28C64B allows 1 to 64 bytes of data
to be written into the device during a single internal programming period. A page write
operation is initiated in the same manner as a byte write; after the first byte is written, it
can then be followed by 1 to 63 additional bytes. Each successive byte must be loaded
within 150 µs (t
BLC
) of the previous byte. If the t
BLC
limit is exceeded, the AT28C64B will
cease accepting data and commence the internal programming operation. All bytes dur-
ing a page write operation must reside on the same page as defined by the state of the
A6 to A12 inputs. For each WE
high to low transition during the page write operation, A6
to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes
may be loaded in any order and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary cycling of other bytes within
the page does not occur.
DATA POLLING: The AT28C64B features DATA
Polling to indicate the end of a write
cycle. During a byte or page write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented on I/O
7
. Once the write
cycle has been completed, true data is valid on all outputs, and the next write cycle may
begin. DATA
Polling may begin at any time during the write cycle.
TOGGLE BIT: In addition to DATA
Polling, the AT28C64B provides another method for
determining the end of a write cycle. During the write operation, successive attempts to
read data from the device will result in I/O
6
toggling between one and zero. Once the
write has completed, I/O
6
will stop toggling, and valid data will be read. Toggle bit read-
ing may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during
transitions of the host system power supply. Atmel has incorporated both hardware and
software features that will protect the memory against inadvertent writes.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent
writes to the AT28C64B in the following ways: (a) V
CC
sense – if V
CC
is below 3.8 V (typ-
ical), the write function is inhibited; (b) V
CC
power-on delay – once V
CC
has reached
3.8 V, the device will automatically time out 5 ms (typical) before allowing a write; (c)
write inhibit – holding any one of OE
low, CE high, or WE high inhibits write cycles; and
(d) noise filter – pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate
a write cycle.
SOFTWARE DATA PROTECTION: A software controlled data protection feature has
been implemented on the AT28C64B. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by
the user; the AT28C64B is shipped from Atmel with SDP disabled.
SDP is enabled by the user issuing a series of three write commands in which three
specific bytes of data are written to three specific addresses (See “Software Data Pro-
