LTC6915
15
6915fb
operaTion
Settling Time
The sampling rate is 3kHz and the input sampling period
during which C
S
is charged to the input differential voltage,
V
IN
, is approximately 150µs. First assume that on each
input sampling period, C
S
is charged fully to V
IN
. Since
C
S
= C
H
(= 1000pF), a change in the input will settle to
N bits of accuracy at the op amp noninverting input after
N clock cycles or 333µs(N). The settling time at the OUT
pin is also affected by the internal op amp. Since the gain
bandwidth of the internal op amp is typically 200kHz, the
settling time is dominated by the switched-capacitor front
end for gains below 100 (see the Low Gain Settling Time
vs Settling Accuracy and the Settling Time vs Gain graphs
in the Typical Performance Characteristics section). In ad-
dition, the worst case settling time after a device-enable
(active low on Pin 1 of a GN package) is equal to the settling
due to the gain plus the input settling time (333µs • N).
For example, if an LTC6915 is enabled with a logic high on
Pin 1 then, the maximum settling time to 10 bits of ac-
curacy (0.1%) and a gain equal to 100 is 8.33ms ([333µs
• 1024] + 5ms).
Input Current
Whenever the differential input V
IN
changes, C
H
must be
charged up to the new input voltage via C
S
. This results
in an input charging current during each input sampling
period. Eventually, C
H
and C
S
will reach V
IN
and ideally,
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on C
S
every cycle even if V
IN
is a DC
voltage. For example, the parasitic bottom plate capacitor
on C
S
must be charged from the voltage on the REF pin to
the voltage on the IN
–
pin every cycle. The resulting input
charging current decays exponentially during each input
sampling period with a time constant equal to R
S
C
S
. If the
voltage disturbance due to these currents settles before
the end of the sampling period, there will be no errors due
to source resistance or the source resistance mismatch
between IN
+
and IN
–
. With R
S
less than 10k, no DC errors
occur due to input current mismatch.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from non-zero source resistance in the inputs. If there
are no large capacitors across the inputs, the amplifier is
less sensitive to source resistance and source resistance
mismatch. When large capacitors are placed across the
inputs, the input charging currents are placed across
the inputs. The input charging currents described above
result in larger DC errors, especially with source resistor
mismatches.
Power Supply Bypassing
In a dual supply operation, connect a 0.1µF bypass ca-
pacitor from each power supply pin (V
+
and V
–
) to an
analog round plance surrounding an LTC6915. The bypass
capacitor trace to the supply pins must be less than
0.2 inches (an X7R or X5R capacitor type is recommended).
In single supply operation, connect the V
–
pin to the analog
ground plane and bypass the V
+
pin.
Shutdown Modes
The IC has two shutdown modes, hardware shutdown and
software shutdown. When SHDN is tied to V
+
, the IC is in
hardware shutdown mode. During this shutdown mode,
the gain setting digital interface (serial or parallel) and the
main op amp are both disabled, thus the PGA dissipates
very small supply current (see the Electrical Characteristic
table). When SHDN is floating, an internal current source
will pull it down to V
–
. The digital interface is turned on to
read the gain setting codes. The IC is in normal amplifica-
tion mode as long as the gain control code is other than
0000. If the gain control code is 0000, the IC operates in
software shutdown mode, i.e., the main op amp is turned
off so that the PGA dissipates less power. The DFN package
does not have hardware shutdown.
Setting the Voltage at the REF Pin
The current coming out of the REF pin may affect the
reference voltage at the REF pin (V
REF
). If V
REF
is set by
a resistive divider then the V
REF
voltage is a function of
the V
OUT
voltage (see Figure 5). In order to minimize the
V
REF
variations, the total resistance of R1 plus R2 should
be much less than 32k (5k or less) or use a voltage refer-
ence to set V
REF
.
Figure 5
–
+
REF
I
REF
=
V
OUT
– V
REF
32k
V
OUT
V
+
V
–
R1
R2
LTC6915
R = 32k
6915 F05
V
V
R
V
k
V
R
RR k
REF
OUT
=+ +
+
12
12
32
32
–
•( )
V
REF
0.1µF
OUT
