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MC74VHCT573ADWR2

P1-P3P4-P6P7-P7
MC74VHCT573A
http://onsemi.com
4
TIMING REQUIREMENTS (Input t
r
= t
f
= 3.0ns)
Symbol
Parameter Test Conditions
T
A
= 25°C T
A
= − 40 to 85°C
Unit
Typ Limit Limit
t
w(h)
Minimum Pulse Width, LE V
CC
= 5.0 ±0.5V 6.5 8.5 ns
t
su
Minimum Setup Time, D to LE V
CC
= 5.0 ± 0.5V 1.5 1.5 ns
t
h
Minimum Hold Time, D to LE V
CC
= 5.0 ± 0.5V 3.5 3.5 ns
ORDERING INFORMATION
Device Package Shipping
†
MC74VHCT573ADWG SOIC−20WB
(Pb−Free)
38 Units / Rail
MC74VHCT573ADWRG SOIC−20WB
(Pb−Free)
1000 / Tape & Reel
MC74VHCT573ADTG TSSOP−20* 75 Units / Rail
MC74VHCT573ADTRG TSSOP−20* 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
Figure 3. Switching Waveform Figure 4. Switching Waveform
LE
t
PLH
t
PHL
Q
t
w
GND
t
PHL
Q
D
t
PLH
1.5V
1.5V
3V
V
OL
V
OH
GND
3V
V
OH
V
OL
1.5V
1.5V
OE
Q
Q 1.5V
t
PZL
t
PLZ
t
PZH
t
PHZ
3V
HIGH
IMPEDANCE
V
OL
+0.3V
V
OH
-0.3V
HIGH
IMPEDANCE
1.5V
1.5V
GND
Figure 5. Switching Waveform Figure 6. Switching Waveform
D
LE
3V
GND
GND
VALID
t
h
t
su
3V
1.5V
1.5V
MC74VHCT573A
http://onsemi.com
5
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 7. Test Circuit Figure 8. Test Circuit
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 kW
Figure 9. Expanded Logic Diagram
D
LE
Q
D0
2
19
Q0
D
LE
Q
D1
3
18
Q1
D
LE
Q
D2
4
17
Q2
D
LE
Q
D3
5
16
Q3
D
LE
Q
D4
6
15
Q4
D
LE
Q
D5
7
14
Q5
D
LE
Q
D6
8
13
Q6
D
LE
Q
D7
9
12
Q7
LE
OE
11
1
MC74VHCT573A
http://onsemi.com
6
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
110
1120
PIN 1
IDENT
A
B
−T−
0.100 (0.004)
C
D
G
H
SECTION N−N
K
K1
JJ1
N
N
M
F
−W−
SEATING
PLANE
−V−
−U−
S
U
M
0.10 (0.004) V
S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
--- ---
S
U0.15 (0.006) T
7.06
16X
0.36
16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
P1-P3P4-P6P7-P7

MC74VHCT573ADWR2

Mfr. #:
Buy MC74VHCT573ADWR2
Manufacturer:
ON Semiconductor
Description:
IC LATCH OCTAL D 3ST 20SOIC
Lifecycle:
New from this manufacturer.
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