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IXS839AQ2

P1-P3P4-P6P7-P9P10-P11
IXYS
4
IXS839 / IXS839A / IXS839B
Electrical Characteristics
Power Supply Terminals T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
<
26V
Parameter Symbol Conditions Min Typ Max Unit
Analog Supply
Voltage Range
V
DD
V
DD
4.5
5.5 V
High Gate Driver
Supply Voltage Range
V
BST -
V
SW
4.5 5.5 V
Low Gate Driver
Supply Voltage Range
V
DD
-
V
PGND
4.5 5.5 V
Floating Supply
Voltage Range
V
SW
-
V
PGDN
0.0 24.0 V
Analog Supply
Current
I
DD
Normal Mode
PWM = V
PGND
2 4 mA
IXS839/839B 0.5 1
High Gate Driver
Supply Current
I
BST
Normal Mode
PWM = V
PGND
IXS839A 1.5
mA
IXS839/839B 10
Analog Supply
Current
I
DD_Shutdown
Shut Down Mode,
LSD
= V
DD
,
SD
= PWM = V
PGND
IXS839A 50
µA
High Gate Driver
Supply Current
I
BST_Shutdown
Shut Down Mode
LSD
= PWM = V
PGND
<1 10
µA
Digital Input Terminals
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
<
26V
Parameter Symbol Conditions Min Typ Max Unit
Input Leakage Current I
IN
PWM = V
PGND
LSD = SD = V
DD
-1 1
µA
Input pull-down Current
PWM = V
DD
2 10 100
µA
Input pull-up Current
__
SD = V
PGND
-2 -10 -100
µA
Input pull-up Current
___
LSD = V
PGND
-2 -10 -100
µA
Minimum High Level
Input Voltage
V
IH
2.0 V
Maximum Low Level
Input Voltage
V
IL
0.8 V
UVLO Circuit
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
<
26V
Parameter Symbol Conditions Min Typ Max Unit
V
DD
Rising Threshold UVOL
RISE
4.2 4.4 4.5 V
V
DD
Falling Threshold UVOL
FALL
3.9 4.25 4.5 V
Delay Circuit
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
<
26V
Parameter Symbol Conditions Min Typ Max Unit
Upper Gate-Driver Turn
on Delay Time with
respect to external delay
capacitor
t
DLY
Capacitor C
DLY
(pF) from DLY
pin to PGND
0.5 nS/pF
IXYS
5
IXS839 / IXS839A / IXS839B
Electrical Characteristics
High Side Gate Driver Circuit
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
<
26V
Parameter Symbol Conditions Min Typ Max Unit
High Side Gate-Driver
On-Resistance, Sourcing
Current
R
HGD_SRC
V
BST
– V
SW
= 4.6V 2.2 Ω
High Side Gate-Driver
On-Resistance, Sinking
Current
R
HGD_SNK
V
BST
– V
SW
= 4.6V 1.2 Ω
High Side Gate-Driver
(1)
Rise-Time
t
R_HGD
C
LOAD
= 3nF
T
R_HGD
measured from 10% to
90% of (V
HGD
- V
SW
)
20 nS
High Side Gate-Driver
(1)
Fall-Time
t
F_HGD
C
LOAD
= 3nF
T
F_HGD
measured from 90% to
10% of (V
HGD
- V
SW
)
15 nS
35 nS
Propagation Delay
(1)
t
PD_HGD1
t
PD_HGD2
C
LOAD_HGD
= C
LOAD_LGD
= 3nF
C
DLY
= 0pF
50 nS
Low Side Gate Driver Circuit
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
<
26V
Parameter Symbol Conditions Min Typ Max Unit
Low Side Gate-Driver
On-Resistance, Sourcing
Current
R
LGD_SRC
V
DD
– V
PGND
= 4.6V 2 Ω
Low Side Gate-Driver
On-Resistance, Sinking
Current
R
LGD_SNK
V
DD
– V
PGND
= 4.6V 1 Ω
Low Side Gate-Driver
(1)
Rise-Time
t
R_LGD
C
LOAD
= 3nF
T
R_LGD
measured from 10% to
90% of (V
LGD
– V
PGND
)
18 nS
Low Side Gate-Driver
(1)
Fall-Time
t
F_LGD
C
LOAD
= 3nF
T
F_LGD
measured from 90% to
10% of (V
LGD
- V
SW
)
12 nS
60 nS
Propagation Delay
(1)
t
PD_LGD1
t
PD_LGD2
C
LOAD_HGD
= C
LOAD_LGD
= 3nF
C
DLY
= 0pF
20 nS
Shut Down Circuit Characteristics
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
<
26V
Parameter Symbol Conditions Min Typ Max Unit
Propagation Delay
(2)
t
PD_LGDSD1
25 50 nS
Propagation Delay
(2)
t
PD_LGDSD2
10 20 nS
Propagation Delay
(3)
t
PD_GDSD1
400 800 nS
Propagation Delay
(3)
t
PD_GDSD2
800 1200 nS
*Notes:
(1) See Timing Diagram in Figure 4
(2) See Timing Diagram in Figure 5
(3) See Timing Diagram in Figure 6
IXYS
6
IXS839 / IXS839A / IXS839B
Figure 4. Non-Overlap Timing Diagram for IXS839/839A/839B
PWM
tpd_lgd2
LGD
HGD-SW
tf_lgd
tpd_lgd1
tpd_hgd2
tr_hgd
tr_lgd
tf_hgd
tpd_hgd1
10%
90%
90%
10%
___ __
Figure 5. LSD Propagation Delay Timing Figure 6. SD Propagation Delay Timing
for IXS839A/B for IXS839A/B
tpd_lgdsd2
tpd_lgdsd1
LGD
LSD
10%
90%
tpd_gdsd2
tpd_gdsd1
LGD/HGD
SD
10%
90%
P1-P3P4-P6P7-P9P10-P11

IXS839AQ2

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IC MOSFET DRIVER SYNC BUCK 10QFN
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