Si5018-EVB
2 Rev. 1.0
Functional Description
The evaluation board simplifies characterization of the
Si5018 OC-48, STM-16, and 2.7 Gbps FEC clock and
data recovery (CDR) device by providing access to all of
the Si5018 I/Os. Device performance can be evaluated
by following the Test Configuration section below.
Specific performance metrics include jitter tolerance,
jitter generation, and jitter transfer.
Power Supply
The evaluation board requires one 2.5 V supply. Supply
filtering is placed on the board to filter typical system
noise components, however, initial performance testing
should use a linear supply capable of supplying 2.5 V
±5% dc.
CAUTION: The evaluation board is designed so that the
body of the SMA jacks and GND are shorted. Care must
be taken when powering the PCB at potentials other
than GND at 0.0 V and VDD at 2.5 V relative to chassis
GND.
Self-Calibration
The Si5018 device provides an internal self-calibration
function that optimizes the loop gain parameters within
the internal DSPLL
TM
. Self-calibration is initiated by a
high-to-low transition of the PWRDN/CAL signal while a
valid reference clock is supplied to the REFCLK input.
On the Si5018-EVB board, a voltage detector IC is
utilized to initiate self-calibration. The voltage detector
drives the PWRDN/CAL signal low after the supply
voltage has reached a specific voltage level. This circuit
is described in Silicon Laboratories application note
AN42. On the Si5018-EVB, the PWRDN/CAL signal is
also accessible via a jumper located in the lower left-
hand corner of the evaluation board. PWRDN/CAL is
wired to the signal post adjacent to the 2.5 V post.
Device Powerdown
The CDR can be powered down via the PWRDN/CAL
signal. When asserted the evaluation board will draw
minimal current. PWRDN/CAL is controlled via one
jumper located in the lower left-hand corner of the
evaluation board. PWRDN/CAL is wired to the signal
post adjacent to the 2.5 V post.
CLKOUT, DATAOUT, DATAIN
These high-speed I/Os are wired to the board perimeter
on 30 mil (0.030 inch) 50 Ω microstrip lines to the end-
launch SMA jacks as labeled on the PCB. These I/Os
are ac coupled to simplify direct connection to a wide
array of standard test hardware. Because each of these
signals are differential both the positive (+) and negative
(–) terminals must be terminated to 50 Ω. Terminating
only one side will adversely degrade the performance of
the CDR. The inputs are terminated on the die with 50 Ω
resistors.
To improve the DATAOUT eye-diagram, short 100 Ω
transmission line segments precede the 50 Ω high-
speed traces. These segments increase the interface
bandwidth from the chip to the 50 Ω traces and reduce
data inter-symbol-interference. Please refer to Silicon
Laboratories application note AN43 for more details.
Note: The 50 Ω termination is for each terminal/side of a dif-
ferential signal, thus the differential termination is actu-
ally 50 Ω +50Ω =100Ω.
REFCLK
REFCLK is used to center the frequency of the
DSPLL™ so that the device can lock to the data. Ideally
the REFCLK frequency should be 1/128th, 1/32nd, or
1/16th the VCO frequency and must have a frequency
accuracy of ±100 PPM. Internally, the CDR
automatically recognizes the REFCLK frequency within
one of these three frequency ranges. Typical REFCLK
frequencies are given in Table 1. REFCLK is ac coupled
to the SMA jacks located on the top side of the
evaluation board.
Loss-of-Lock (LOL)
LOL is an indicator of the relative frequency between
the data and the REFCLK. LOL will assert when the
frequency difference is greater than ±600 PPM. In order
to prevent LOL from de-asserting prematurely, there is
hysterisis in returning from the out-of-lock condition.
LOL will be de-asserted when the frequency difference
is less than ±300 PPM.
LOL is wired to a test point which is located on the
upper right-hand side of the evaluation board.
Test Configuration
The three critical tests that are typically performed on a
CDR device are jitter transfer, jitter tolerance, and jitter
generation. By connecting the Si5018 Evaluation Board
as shown in Figure 1, all three measurements can be
easily made.
REFCLK should be within ±100 PPM of the frequency
selected from Table 1. PWRDN/CAL must be
unjumpered.
Table 1. Typical REFCLK Frequencies
SONET/SDH
Gigabit
Ethernet
SONET/
SDH with
15/14 FEC
Ratio of
VCO to
REFCLK
19.44 MHz 19.53 MHz 20.83 MHz 128
77.76 MHz 78.125 MHz 83.31 MHz 32
155.52 MHz 156.25 MHz 166.63 MHz 16
