AD585SQ/883B

AD585
REV. A
–3–
Figure 2. Acquisition Time vs. Hold Capacitance
(10 V Step to 0.01%)
ABSOLUTE MAXIMUM RATINGS
Supplies (+V
S
, –V
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
S
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
S
R
IN
, R
FB
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
S
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering) . . . . . . . . . . . . . . . . . . . 300°C
Output Short Circuit to Ground . . . . . . . . . . . . . . . . Indefinite
TTL Logic Reference Short
Circuit to Ground . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
AD585
REV. A
–4–
SAMPLED DATA SYSTEMS
In sampled data systems there are a number of limiting factors
in digitizing high frequency signals accurately. Figure 9 shows
pictorially the sample-and-hold errors that are the limiting fac-
tors. In the following discussions of error sources the errors will
be divided into the following groups: 1. Sample-to-Hold Transi-
tion, 2. Hold Mode and 3. Hold-to-Sample Transition.
Figure 9. Pictorial Showing Various S/H Characteristics
SAMPLE-TO-HOLD TRANSITION
The aperture delay time is the time required for the sample-and-
hold amplifier to switch from sample to hold. Since this is effec-
tively a constant then it may be tuned out. If however, the
aperture delay time is not accounted for then errors of the mag-
nitude as shown in Figure 10 will result.
Figure 10. Aperture Delay Error vs. Frequency
To eliminate the aperture delay as an error source the sample-
to-hold command may be advanced with respect to the input
signal .
Once the aperture delay time has been eliminated as an error
source then the aperture jitter which is the variation in aperture
delay time from sample-to-sample remains. The aperture jitter is
a true error source and must be considered. The aperture jitter
is a result of noise within the switching network which modu-
lates the phase of the hold command and is manifested in the
variations in the value of the analog input that has been held.
The aperture error which results from this jitter is directly re-
lated to the dV/dT of the analog input.
The error due to aperture jitter is easily calculated as shown be-
low. The error calculation takes into account the desired accu-
racy corresponding to the resolution of the N-bit A/D converter.
f
MAX
=
2
–(N +1)
π(Aperture Jitter)
For an application with a 10-bit A/D converter with a 10 V full
scale to a 1/2 LSB error maximum.
f
MAX
=
2
–(10 +1)
π(0.5 ×10
–9
)
f
MAX
= 310.8 kHz.
For an application with a 12-bit A/D converter with a 10 V full
scale to a 1/2 LSB error maximum:
f
MAX
=
2
–(12 +1)
π(0.5 ×10
–9
)
f
MAX
= 77.7 kHz.
Figure 11 shows the entire range of errors induced by aperture
jitter with respect to the input signal frequency.
Figure 11. Aperture Jitter Error vs. Frequency
Sample-to-hold offset is caused by the transfer of charge to the
holding capacitor via the gate capacitance of the switch when
switching into hold. Since the gate capacitance couples the
switch control voltage applied to the gate on to the hold capaci-
tor, the resulting sample-to-hold offset is a function of the logic
level .
The logic inputs were designed for application flexibility and,
therefore, a wide range of logic thresholds. This was achieved by
using a differential input stage for HOLD and
HOLD. Figure 1
shows the change in the sample-to-hold offset voltage based
upon an independently programmed reference voltage. Since
the input stage is a differential configuration, the offset voltage
is a function of the control voltage range around the pro-
grammed threshold voltage.
The sample-to-hold offset can be reduced by adding capacitance
to the internal 100 pF capacitor and by using
HOLD instead of
HOLD. This may be easily accomplished by adding an external
capacitor between Pins 7 and 8. The sample-to-hold offset is
then governed by the relationship:
S/H Offset (V ) =
Charge pC
()
C
H
Total ( pF )
AD585
REV. A
–5–
For the AD585 in particular it becomes:
S/H Offset (V ) =
0.3 pC
100 pF + C
EXT
()
The addition of an external hold capacitor also affects the acqui-
sition time of the AD585. The change in acquisition time with
respect to the C
EXT
is shown graphically in Figure 2.
HOLD MODE
In the hold mode there are two important specifications that
must be considered; feedthrough and the droop rate. Feedthrough
errors appear as an attenuated version of the input at the output
while in the hold mode. Hold-Mode feedthrough varies with fre-
quency, increasing at higher frequencies. Feedthrough is an im-
portant specification when a sample and hold follows an analog
multiplexer that switches among many different channels.
Hold-mode droop rate is the change in output voltage per unit
of time while in the hold mode. Hold-mode droop originates as
leakage from the hold capacitor, of which the major leakage
current contributors are switch leakage current and bias current.
The rate of voltage change on the capacitor dV/dT is the ratio of
the total leakage current I
L
to the hold capacitance C
H
.
Droop Rate =
dV
OUT
dT
(Volts/Sec) =
I
L
( pA)
C
H
( pF)
For the AD585 in particular;
Droop Rate =
100 pA
100 pF +(C
EXT
)
Additionally the leakage current doubles for every 10°C increase
in temperature above 25°C; therefore, the hold-mode droop rate
characteristic will also double in the same fashion. The hold-mode
droop rate can be traded-off with acquisition time to provide the
best combination of droop error and acquisition time. The tradeoff
is easily accomplished by varying the value of C
EXT
.
Since a sample and hold is used typically in combination with
an A/D converter, then the total droop in the output voltage has
to be less than 1/2 LSB during the period of a conversion. The
maximum allowable signal change on the input of an A/D
converter is:
V max =
Full -Scale Voltage
2
N +1
()
Once the maximum V is determined then the conversion time
of the A/D converter (T
CONV
) is required to calculate the maxi-
mum allowable dV/dT.
dV
dt
max =
V max
T
CONV
The maximum
dV max
dT
as shown by the previous equation is
the limit not only at 25°C but at the maximum expected operat-
ing temperature range. Therefore, over the operating temperature
range the following criteria must be met (T
OPERATION
–25°C)
= T.
dV 25°C
dT
× 2
T °C
()
10°C
dV max
dT
HOLD-TO-SAMPLE TRANSITION
The Nyquist theorem states that a band-limited signal which is
sampled at a rate at least twice the maximum signal frequency
can be reconstructed without loss of information. This means
that a sampled data system must sample, convert and acquire
the next point at a rate at least twice the signal frequency. Thus
the maximum input frequency is equal to
f
MAX
=
1
2 T
ACQ
+T
CONV
+T
AP
()
Where T
ACQ
is the acquisition time of the sample-to-hold
amplifier, T
AP
is the maximum aperture time (small enough to
be ignored) and T
CONV
is the conversion time of the A/D
converter.
DATA ACQUISITION SYSTEMS
The fast acquisition time of the AD585 when used with a high
speed A/D converter allows accurate digitization of high fre-
quency signals and high throughput rates in multichannel data
acquisition systems. The AD585 can be used with a number of
different A/D converters to achieve high throughput rates. Fig-
ures 12 and 13 show the use of an AD585 with the AD578 and
AD574A.
Figure 12. A/D Conversion System, 117.6 kHz Throughput
58.8 kHz max Signal Input
Figure 13. 12-Bit A/D Conversion System, 26.3 kHz
Throughput Rate, 13.1 kHz max Signal Input

AD585SQ/883B

Mfr. #:
Manufacturer:
Description:
Sample & Hold Amplifiers IC HI SPD SAMPLE/ HOLD AMP
Lifecycle:
New from this manufacturer.
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