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83948AYILF

P1-P3P4-P6P7-P9P10-P12P13-P13
1©2016 Integrated Device Technology, Inc May 19, 2016
1
0
D
Q
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
CLK_EN
CLK_SEL
OE
LVCMOS_CLK
CLK
nCLK
Pulldown
Pullup
Pullup
Pullup
Pullup
Pullup
General Description
The 83948I is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL
Fanout Buffer and a member of the family of High Performance
Clock Solutions from IDT. The 83948I has two selectable clock
inputs. The CLK, nCLK pair can accept most standard differential
input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL
input levels. The low impedance LVCMOS/LVTTL outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
The 83948I is characterized at full 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics make the
83948I ideal for those clock distribution applications demanding
well defined performance and repeatability.
Features
• Twelve LVCMOS/LVTTL outputs
• Selectable differential CLK/nCLK or LVCMOS/LVTTL clock
input
• CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
• Maximum output frequency: 250MHz
• Output skew: 350ps (maximum)
• Part-to-part skew: 1.5ns (maximum)
• 3.3V core, 3.3V output
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For drop in replacement part use 83948i-147
83948I
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
GND
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
Q11
V
DDO
Q10
GND
Q9
VDDO
Q8
GND
Q0
V
DDO
Q1
GND
Q2
V
DDO
Q3
GND
Pin Assignment
Block Diagram
83948I
Datasheet
Low Skew, 1-to-12 Differential-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
2©2016 Integrated Device Technology, Inc May 19, 2016
83948I Datasheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3A. Clock Select Function Table
Number Name Type Description
1 CLK_SEL Input Pullup
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
2 LVCMOS_CLK Input Pullup Single-ended clock input. LVCMOS/LVTTL interface levels.
3 CLK Input Pullup Non-inverting differential clock input.
4 nCLK Input Pulldown Inverting differential clock input.
5 CLK_EN Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels.
6 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels.
7V
DD
Power Positive supply pin.
8, 12, 16,
20, 24, 28, 32
GND Power Power supply ground.
9, 11, 13,
15, 17, 19,
21, 23, 25,
27, 29, 31
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
10, 14, 18,
22, 26, 30
V
DDO
Power Output supply pins.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
C
PD
Power Dissipation Capacitance
(per output)
25 pF
R
OUT
Output Impedance 7
Control Input Clock
CLK_SEL CLK/nCLK LVCMOS_CLK
0 Selected De-selected
1 De-selected Selected
3©2016 Integrated Device Technology, Inc May 19, 2016
83948I Datasheet
Table 3B. Clock Input Function Table
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= V
DDO
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Inputs Outputs
Input to Output Mode PolarityCLK_SEL LVCMOS_CLK CLK nCLK Q[0:11]
0 – 0 1 LOW Differential to Single-Ended Non-Inverting
0 – 1 0 HIGH Differential to Single-Ended Non-Inverting
0 – 0 Biased; NOTE 1 LOW Single-Ended to Single-Ended Non-Inverting
0 – 1 Biased; NOTE 1 HIGH Single-Ended to Single-Ended Non-Inverting
0 – Biased; NOTE 1 0 HIGH Single-Ended to Single-Ended Inverting
0 – Biased; NOTE 1 1 LOW Single-Ended to Single-Ended Inverting
1 0 – – LOW Single-Ended to Single-Ended Non-Inverting
1 1 – – HIGH Single-Ended to Single-Ended Non-Inverting
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.0 3.3 3.6 V
V
DDO
Output Supply Voltage 3.0 3.3 3.6 V
I
DD
Power Supply Current 55 mA
P1-P3P4-P6P7-P9P10-P12P13-P13

83948AYILF

Mfr. #:
Buy 83948AYILF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 12 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
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