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SSM3J56MFV,L3F

P1-P3P4-P6
SSM3J56MFV
2014-03-01
1
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSⅥ)
SSM3J56MFV
○ Load Switching Applications
• 1.2 V drive
• Low ON-resistance: R
DS(ON)
= 390 mΩ (max) (@V
GS
= -4.5 V)
R
DS(ON)
= 480 mΩ (max) (@V
GS
= -2.5 V)
R
DS(ON)
= 660 mΩ (max) (@V
GS
= -1.8 V)
R
DS(ON)
= 900 mΩ (max) (@V
GS
= -1.5 V)
R
DS(ON)
= 4000 mΩ (max) (@V
GS
= -1.2 V)
Absolute Maximum Ratings
(Ta = 25°C)
Characteristic Symbol Rating Unit
Drain-Source voltage V
DSS
-20 V
Gate-Source voltage V
GSS
± 8 V
DC I
D
(Note 1) -800
Drain current
Pulse I
DP
(Note 1) -1600
mA
P
D
(Note 2) 150
P
D
(Note 3) 500
Power dissipation
t < 5s 800
mW
Channel temperature T
ch
150 °C
Storage temperature range T
stg
−55 to 150 °C
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in temperature,
etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.)
are within the absolute maximum ratings.
Please design the appropriate reliability upon reviewing the Toshiba
Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual
reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1: The channel temperature should not exceed 150°C during use.
Note 2: Mounted on a FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.585 mm
2
)
Note 3: Mounted on a FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm
2
)
Marking Equivalent Circuit
(top view)
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
Thermal resistance R
th (ch-a)
and Power dissipation P
D
vary depending on board material, board area, board thickness
and pad area. When using this device, please take heat dissipation into consideration.
Unit: mm
JEDEC ―
JEITA ―
TOSHIBA 2-1L1B
Weight: 1.5mg (typ.)
PW
1 2
3
1 2
3
1.Gate
2.Source
3.Drain
VESM
Start of commercial production
2011-05
SSM3J56MFV
2014-03-01
2
Electrical Characteristics
(Ta = 25°C)
Characteristic Symbol Test Conditions Min Typ. Max Unit
V
(BR) DSS
I
D
= -1 mA, V
GS
= 0 V -20 ⎯ ⎯ V
Drain-source breakdown voltage
V
(BR) DSX
I
D
= -1 mA, V
GS
= 5 V .(Note 5) -15 ⎯ ⎯ V
Drain cut-off current I
DSS
V
DS
= -20 V, V
GS
= 0 V ⎯ ⎯ -1 μA
Gate leakage current I
GSS
V
GS
= ±8 V, V
DS
= 0 V ⎯ ⎯ ±1 μA
Gate threshold voltage V
th
V
DS
= -3 V, I
D
= -1 mA -0.3 ⎯ -1.0 V
Forward transfer admittance ⏐Y
fs
⏐ V
DS
= -3 V, I
D
= -100 mA (Note 4) 0.5 1.0 ⎯ S
I
D
= -800 mA, V
GS
= -4.5 V (Note 4) ⎯ 310 390
I
D
= -500 mA, V
GS
= -2.5 V (Note 4) ⎯ 380 480
I
D
= -200 mA, V
GS
= -1.8 V (Note 4) ⎯ 470 660
I
D
= -100 mA, V
GS
= -1.5 V (Note 4) ⎯ 560 900
Drain–source ON-resistance R
DS (ON)
I
D
= -10 mA, V
GS
= -1.2 V (Note 4) ⎯ 770 4000
mΩ
Input capacitance C
iss
⎯ 100 ⎯
Output capacitance C
oss
⎯ 16 ⎯
Reverse transfer capacitance C
rss
V
DS
= -10 V, V
GS
= 0 V, f = 1 MHz
⎯ 10 ⎯
pF
Turn-on time t
on
⎯ 8 ⎯
Switching time
Turn-off time t
off
V
DD
= -10 V, I
D
= -200 mA
V
GS
= 0 to -2.5 V, R
G
= 50 Ω
⎯ 26 ⎯
ns
Total gate charge Q
g
⎯ 1.6 ⎯
Gate-source charge Q
gs1
⎯ 0.2 ⎯
Gate-drain charge Q
gd
V
DD
= -10 V, I
D
= -800 mA,
V
GS
= -4.5 V
⎯ 0.4 ⎯
nC
Drain-source forward voltage V
DSF
I
D
= 800 mA, V
GS
= 0 V (Note 4) ⎯ 0.9 1.2 V
Note 4: Pulse test
Note 5: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode.
Note that the drain-source breakdown voltage is lowered in this mode.
Switching Time Test Circuit
(a) Test Circuit (b) V
IN
Notice on Usage
V
th
can be expressed as the voltage between gate and source when the low operating current value is I
D
= -1 mA for
this product. For normal switching operation, V
GS
(on)
requires a higher voltage than V
th
and V
GS (off)
requires a lower
voltage than V
th.
(The relationship can be established as follows: V
GS (off)
< V
th
< V
GS (on).
)
Take this into consideration when using the device.
(c) V
OUT
V
DD
= -10 V
R
G
= 50 Ω
Duty ≤ 1%
V
IN
: t
r
, t
f
< 5 ns
Common Source
Ta = 25°C
IN
0
−2.5V
10 μs
V
DD
OUT
R
G
R
L
t
on
10%
90%
−2.5 V
0 V
90%
10%
t
off
t
r
t
f
V
DS
(
ON
)
V
DD
SSM3J56MFV
2014-03-01
3
Gate–source voltage V
GS
(V)
I
D
– V
GS
Drain current I
D
(A)
-10
0
-0.1
-1
-0.001
-0.01
-0.0001
Common Source
V
DS
= -3 V
Pulse test
Ambient temperature Ta (°C)
R
DS (ON)
– Ta
Drain–source ON-resistance
R
DS (ON)
(Ω)
−50 0 50 150 100
Drain–source voltage V
DS
(V)
I
D
– V
DS
Drain current I
D
(A)
0
0
-0.5 -1.0 -1.5
Common Source
Ta = 25 °C
Pulse test
Drain–source ON-resistance
R
DS (ON)
(Ω)
0 -2
-4
-6
Gate–source voltage V
GS
(V)
0
R
DS (ON)
– V
GS
-8
I
D
= -10 mA
Common Source
Pulse test
R
DS (ON)
– I
D
Drain current I
D
(A)
Drain–source ON-resistance
R
DS (ON)
(Ω)
-1.5
-1.0
-1.8 V
V
GS
= -1.2 V
-2.5 V
-2.0
-4.5 V
-2.0
-1.0
-25 °C
Ta = 100 °C
25 °C
1.2
-25 °C
25 °C
1.6
Ta = 100 °C
0.8
-2.0
0
-1.0
0
-1.5
1.6
0.4
0.8
V
GS
= -4.5 V
-1.5 V
-2.5 V
-1.8 V
-0.5
Common Source
Ta = 25 °C
Pulse test
0
1.6
0.4
I
D
= -800 mA / V
GS
= -4.5 V
-10 mA / -1.2 V
-500 mA / -2.5 V
-200 mA / -1.8 V
1.2
Common Source
Pulse test
-0.5
-1.5 V
0.4
12
-1.2 V
Drain–source ON-resistance
R
DS (ON)
(Ω)
0 -2 -4 -6
Gate–source voltage V
GS
(V)
0
R
DS (ON)
– V
GS
-8
I
D
= -800 mA
Common Source
Pulse test
1.2
-25 °C
25 °C
1.6
Ta = 100 °C
0.8
0.4
-100 mA / -1.5 V
0.8
P1-P3P4-P6

SSM3J56MFV,L3F

Mfr. #:
Buy SSM3J56MFV,L3F
Manufacturer:
Toshiba
Description:
MOSFET Small Signal MOSFET
Lifecycle:
New from this manufacturer.
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