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AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015
3. Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface directly with the
FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data
from the configuration device without requiring an external intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter.
When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin.
The CE pin also controls the output of the AT17F Series Configurator. If CE is held High after the RESET/OE
reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High,
the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is
reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to
avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
4. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The
program is loaded either automatically upon power-up or on command, depending on the state of the FPGA
mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.
The AT17F Serial Configuration PROM has been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.
5. Control of Configuration
Most connections between the FPGA device and the AT17F Serial Configurator PROM are simple and
self-explanatory.
The DATA output of the AT17F Series Configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17F Series Configurator.
The CEO output of any AT17F Series Configurator drives the CE input of the next Configurator in a
cascade chain of configurator devices.
SER_EN must be connected to V
CC
(except during ISP).
The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low
while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.
PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0] inputs must be tied off
High or Low. If paging is desired, PAGE_EN must be High and the PAGESEL pins must be set to High or
Low such that the desired page is selected (Table 1-2).
6. Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain or for FPGAs requiring larger configuration memories,
cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output
Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and
enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE
on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive
(High) level.
