13
LT1571 Series
Figure 10. LT1571 Lead Temperature
instead of V
BAT
(see Figure 8). The optimum boost voltage
(V
X
) is from 3V to 6V.
Then,
P
IVV
V
V
DRIVER
BAT BAT X
X
IN
=
()( )()
+
()
1
30
55
For example, V
X
= 3.3V,
P
AVV
V
V
W
DRIVER
=
()()()
+
()
=
12 84 33 1
33
30
55 15
0 045
...
.
.
The average I
VX
required is:
P
V
W
V
mA
DRIVER
X
==
0 045
33
14
.
.
Total board area becomes an important factor when the
area of the board drops below about 20 square inches. The
graph in Figure 9 shows thermal resistance vs board area
for 2-layer and 4-layer boards. Note that 4-layer boards
have significantly lower thermal resistance, but both types
show a rapid increase for reduced board areas. Figure 10
shows actual measured lead temperature for chargers
operating at full current. Battery voltage and input voltage
will affect device power dissipation, so the data sheet
power calculations must be used to extrapolate these
readings to other situations.
Vias should be used to connect board layers together.
Planes under the charger area can be cut away from the
rest of the board and connected with vias to form both a
low thermal resistance system and to act as a ground
plane for reduced EMI.
Higher Duty Cycle
Maximum duty cycle for the LT1571-1/LT1571-2 is typi-
cally 90% but this may be too low for some applications.
For example, if an 18V ±3% adapter is used to charge ten
NiMH cells, the charger must put out approximately 15V.
A total of 1.6V is lost in the input diode, switch resistance,
inductor resistance and parasitics so the required duty
Figure 9. LT1571 Thermal Resistance
Figure 8. Lower V
BOOST
BOOST
SW
SENSE
V
X
3V TO 6V
I
VX
1571 F08
LT1571
C1
L1
D2
10µF
+
BOARD AREA (IN
2
)
0
60
55
50
45
40
35
30
25
15 25
1571 F09
510
20 30 35
THERMAL RESISTANCE (°C/W)
GN16, MEASURED FROM AIR AMBIENT
TO DIE USING COPPER LANDS AS
SHOWN ON DATA SHEET
2-LAYER BOARD
4-LAYER BOARD
BOARD AREA (IN
2
)
0
90
80
70
60
50
40
30
20
15 25
1571 F10
510
20 30 35
LEAD TEMPERATURE (°C)
I
CHRG
= 1.3A
V
IN
= 16V
V
BAT
= 8.4V
V
BOOST
= V
BAT
T
A
= 25°C
NOTE: PEAK DIE TEMPERATURE WILL BE
ABOUT 10°C HIGHER THAN LEAD TEMPER-
ATURE AT 1.3A CHARGING CURRENT
2-LAYER BOARD
4-LAYER BOARD
cycle is 15/16.4 = 91.4%. The duty cycle can be extended
to 93% by restricting boost voltage to 5V instead of using
V
BAT
as is normally done. This lower boost voltage V
X
(see
Figure 8) also reduces power dissipation in the LT1571.
APPLICATIO S I FOR ATIO
WUUU
14
LT1571 Series
Figure 13. Critical Electrical and Thermal Path Layer for LT1571-5
Lower Dropout Voltage
For even lower dropout and/or reducing heat on the
board, the input diode D3 can be replaced with a FET (see
Figure 11). Connect a P-channel FET in place of the input
diode with its gate connected to the battery (SENSE pin)
causing the FET to turn off when the input voltage goes
low. The problem is that the gate must be pumped low so
that the FET is fully turned on even when the input is only
a volt or two above the battery voltage. Also there is a turn-
off speed issue. The FET should turn off instantly when the
input is dead shorted to avoid large current surges from
the battery back through the charger into the FET. Gate
capacitance slows turn off, so a small P-FET (Q2) dis-
charges the gate capacitance quickly in the event of an
input short. The body diode of Q2 creates the necessary
pumping action to keep the gate of Q1 low during normal
operation.
Figure 12. High Speed Switching Path
Layout Considerations
Switch rise and fall times are under 10ns for maximum
efficiency. To minimize radiation, the catch diode, SW pin
and input bypass capacitor leads should be kept as short
as possible. A ground plane should be used under the
switching circuitry to prevent interplane coupling and to
act as a thermal spreading path. All ground pins should be
connected to expand traces for low thermal resistance.
The fast-switching high current ground path including the
switch, catch diode and input capacitor should be kept
very short. Catch diode and input capacitor should be
close to the chip and terminated to the same point. This
path contains nanosecond rise and fall times with several
amps of current. The other paths contain only DC and /or
200kHz or 500kHz triwave and are less critical. Figure 12
indicates the high speed, high current switching path.
Figure 13 shows critical path layout.
Figure 11. Replacing the Input Diode
V
X
3V TO 6V
HIGH DUTY CYCLE
CONNECTION
V
IN
1571 F11
C3
L1
D2
D1
Q2
Q1
R
X
50k
Q1: Si4435DY
Q2: TP0610L
C
X
10µF
V
BAT
BOOST
SW
SENSE
V
CC
LT1571
BAT
+
+
APPLICATIO S I FOR ATIO
WUUU
1571 F12
V
BAT
L1
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
SWITCH NODE
C
IN
C
OUT
D1
L1
C
IN
GND
1571 F13
LT1571-5
GND
V
CC2
V
CC1
CAP
PROG
V
C
BAT
GND
GND
SW
BOOST
BAT2
FLAG
SELECT
SENSE
GND
15
LT1571 Series
GN Package
28-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
Dimensions in inches (millimeters) unless otherwise noted.
0.386 – 0.393*
(9.804 – 9.982)
GN28 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
12
3
4
5
6
7
8 9 10 11 12
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
202122232425262728
19
18
17
13 14
16
15
0.016 – 0.050
(0.406 – 1.270)
0.015
± 0.004
(0.38 ± 0.10)
× 45°
0° – 8° TYP
0.0075 – 0.0098
(0.191 – 0.249)
0.053 – 0.069
(1.351 – 1.748)
0.008 – 0.012
(0.203 – 0.305)
0.004 – 0.009
(0.102 – 0.249)
0.0250
(0.635)
BSC
0.033
(0.838)
REF
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
GN16 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
12
3
4
5
6
7
8
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
16
15
14
13
0.189 – 0.196*
(4.801 – 4.978)
12 11 10
9
0.016 – 0.050
(0.406 – 1.270)
0.015
± 0.004
(0.38 ± 0.10)
× 45°
0° – 8° TYP
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
0.004 – 0.0098
(0.102 – 0.249)
0.0250
(0.635)
BSC
0.009
(0.229)
REF

LT1571EGN-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Adj Output CC/CV Batt Charger
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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