874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER
REVISION A 9/18/14
5 ©2014 Integrated Device Technology, Inc.
Table 4C. LVDS DC Characteristics, V
DD
= V
DDO
= 2.5V, T
A
= -40°C to 85°C
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V
DD
= V
DDO
= 2.5V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: Part-to-part skew specification does not guarantee divider synchronization between devices
NOTE 6: If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.
NOTE 7: Measured from SDA rising edge of I
2
C stop command.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 400 460 600 mV
V
OD
V
OD
Magnitude Change 15 94 mV
V
OS
Offset Voltage 1.09 1.15 1.18 V
V
OS
V
OS
Magnitude Change 2 14 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
REF
Input Frequency IN, nIN 500 MHz
f
OUT
Output Frequency
FSEL[1:0] = 00 500 MHz
FSEL[1:0] = 01 250 MHz
FSEL[1:0] = 10
125 MHz
FSEL[1:0] = 11
62.5 MHz
f
SCK
I
2
C Clock Frequency 400 kHz
t
JIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section, measured with
FSEL[1:0] = 00
f
REF
= 100MHz,
Integration Range: 1MHz – 20MHz
0.214 0.260 ps
f
REF
= 125MHz,
Integration Range: 1MHz – 20MHz
0.168 0.208 ps
f
REF
=156.25,
Integration Range: 1MHz – 20MHz
0.124 0.152 ps
t
PD
Propagation Delay; NOTE 1
FSEL[1:0] = 00 1.30 1.89 2.30 ns
FSEL[1:0] = 01 210 2.60 2.80 ns
FSEL[1:0] = 10
2.60 3.33 3.60 ns
FSEL[1:0] = 11
2.90 3.73 4.00 ns
tsk(o) Output Skew; NOTE 2, 3 28 60 ps
tsk(p) Pulse Skew 27 50 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4, 5 600 ps
odc Output Duty Cycle; NOTE 6
Any Frequency 50 %
at f
REF
= 100MHz 48 50 52 %
at f
REF
= 125MHz 48 50 52 %
at f
REF
= 156.25MHz 48 50 52 %
t
PDZ
Output Enable and Disable Time;
NOTE 7
Output enable/disable state from/to
active/inactive
1µs
t
R
/ t
F
Output Rise/ Fall Time 20% to 80% 200 422 650 ps
