Detailed Description
The DG411F/DG412F/DG413F are fault-protected
CMOS analog switches with unique operation and
construction. These switches differ considerably from
traditional fault-protection switches, with several advan-
tages. First, they are constructed with two parallel
FETs, allowing very low on-resistance when the switch
is on. Second, they allow signals on the NO_ or NC_
pins that are within, or slightly beyond, the supply rails
to be passed through the switch to the COM_ terminal
(or vice versa), allowing true rail-to-rail signal operation.
Third, the DG411F/DG412F/DG413F have the same
fault-protection performance on any of the NO_, NC_,
or COM_ switch inputs. Operation is identical for both
fault polarities. The fault protection extends to ±36V
from GND with ±15V supplies.
During a fault condition, the particular overvoltage input
(COM_, NO_, NC_) pin becomes high impedance
regardless of the switch state or load resistance. When
power is removed, the fault protection is still in effect. In
this case, the COM_, NO_, or NC_ terminals are a virtu-
al open circuit. The fault can be up to ±40V with power
off. The switches turn off when V+ is not powered,
regardless of V-.
Pin Compatibility
These switches have identical pinouts to common non-
fault-protected CMOS switches. They allow for carefree
direct replacement in existing printed circuit boards
since the NO_, NC_, and COM_ pins of each switch are
fault protected.
Internal Construction
Internal construction is shown in Figure 1, with the ana-
log signal paths shown in bold. A single NO switch is
shown. The NC configuration is identical except the
logic-level translator becomes an inverter. The analog
switch is formed by the parallel combination of N-chan-
nel FET (N1) and P-channel FET (P1), which are driven
on and off simultaneously according to the input fault
condition and the logic-level state.
Normal Operation
Two comparators continuously compare the voltage on
the COM_, NO_, and NC_ pins with V+ and V-. When
the signal on COM_, NO_, or NC_ is between V+ and
V-, the switch acts normally, with FETs N1 and P1 turn-
ing on and off in response to IN_ signals. The parallel
combination of N1 and P1 forms a low-value resistor
between NO_ (or NC_) and COM_ so that signals pass
equally well in either direction.
Positive Fault Condition
When the signal on NO_ (or NC_) and COM_ exceeds
V+ by about 50mV, the high-fault comparator output is
high, turning off FETs N1 and P1. This makes the NO_
(or NC_) and COM_ pins high impedance regardless of
DG411F/DG412F/DG413F
Quad, Rail-to-Rail, Fault-Protected,
SPST Analog Switches
_______________________________________________________________________________________ 9
Negative-Supply Voltage Input. Connect to GND for single-
supply operation. Bypass with a 0.1µF capacitor to GND.
Positive-Supply Voltage Input. Bypass with a 0.1µF capacitor
to GND.
