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MT18VDDF12872Y-40BJ1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
PDF: 09005aef8074e85b/Source: 09005aef8072fe49 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C64_128x72.fm - Rev. F 9/08 EN
13 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Register and PLL Specifications
Register and PLL Specifications
Notes: 1. Timing and switching specifications for the register listed above are critical for proper oper-
ation of the DDR SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module. Detailed information for this register is available in
JEDEC Standard JESD82.
Table 12: Register Specifications
SSTV16859 devices or equivalent JESD82-4B
Parameter Symbol Pins Condition Min Max Units
DC high-level
input voltage
VIH(DC) Control,
command, address
SSTL_25 VREF(DC) + 150 – mV
DC low-level
input voltage
V
IL(DC) Control,
command, address
SSTL_25 – VREF(DC) - 150 mV
AC high-level
input voltage
VIH(AC) Control,
command, address
SSTL_25 VREF(DC) + 310 VDD mV
AC low-level
input voltage
VIL(AC) Control,
command, address
SSTL_25 – VREF(DC) - 310 mV
Output high voltage V
OH Parity output LVCMOS VDD - 0.2 – V
Output low voltage VOL Parity output LVCMOS – 0.2 V
Input current I
I All pins VI = VDDQ or VSSQ –5.0 +5.0 µA
Static standby I
DD All pins RESET# = VSSQ (IO = 0) – 100 µA
Static operating IDD All pins RESET# = VSSQ;
VI =VIH(AC) or VIL(DC)
IO =0
–Varies by
manufacturer
mA
Dynamic operating
(clock tree)
IDDD n/a RESET# = VDD,
VI =VIH(AC) or VIL(AC),
IO = 0; CK and CK#
switching 50% duty cycle
–Varies by
manufacturer
µA
Dynamic operating
(per each input)
IDDD n/a RESET# = VDD,
VI =VIH(AC) or VIL(AC),
I
O = 0; CK and CK#
switching 50% duty cycle;
One data input switching
at
t
CK/2, 50% duty cycle
–Varies by
manufacturer
µA
Input capacitance
(per device, per pin)
C
I All inputs except
RESET#
VI =VREF ±250mV;
V
DDQ=1.8V
2.5 3.5 pF
Input capacitance
(per device, per pin)
C
I RESET# VI =VDDQ or VSSQ–Varies by
manufacturer
pF
PDF: 09005aef8074e85b/Source: 09005aef8072fe49 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C64_128x72.fm - Rev. F 9/08 EN
14 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Register and PLL Specifications
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC Standard JESD82-1A.
Table 13: PLL Specifications
CVF857 device or equivalent JESD82-1A
Parameter Symbol Min Max Units
DC high-level input voltage V
IH 1.7 VDDQ + 0.3 V
DC low-level input voltage VIL –0.3 0.7 V
Input voltage (limits) V
IN –0.3 VDDQ + 0.3 V
Input differential-pair cross voltage VIX (VDDQ/2) - 0.2 (VDDQ/2) + 0.2 V
Input differential voltage V
ID(DC)0.36 VDDQ + 0.6 V
Input differential voltage V
ID(AC)0.70 VDDQ + 0.6 V
Input current II –10 +10 µA
Dynamic supply current I
DDPD –200µA
Dynamic supply current I
DDQ –300µA
Dynamic supply current IADD –12mA
Input capacitance C
IN 2.0 3.5 pF
Table 14: PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter Symbol Min Max Units
Stabilization time
t
L–100µs
Input clock slew rate
t
slr(i) 1.0 4.0 V/ns
SSC modulation frequency – 30 50 kHz
SSC clock input frequency deviation – 0 –0.50 %
PLL loop bandwidth (–3dB from unity gain) – 2.0 – MHz
PDF: 09005aef8074e85b/Source: 09005aef8072fe49 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF18C64_128x72.fm - Rev. F 9/08 EN
15 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Serial Presence-Detect
Serial Presence-Detect
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
Table 15: Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage VDDSPD 2.3 3.6 V
Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs V
IL –1.0 VDDSPD × 0.3 V
Output low voltage: I
OUT = 3mA VOL –0.4V
Input leakage current: VIN = GND to VDD ILI –10µA
Output leakage current: V
OUT = GND to VDD ILO –10µA
Standby current: SCL = SDA = V
DD - 0.3V; All other inputs = VSS or
V
DD
ISB –30µA
Power supply current: SCL clock frequency = 100 kHz ICC –2.0mA
Table 16: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 – µs
Data-out hold time
t
DH 200 – ns
SDA fall time
t
F–300ns2
SDA rise time
t
R–300ns2
Data-in hold time
t
HD:DAT 0 – µs
Start condition hold time
t
H:STA 0.6 – µs
Clock HIGH period
t
HIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs
t
I–50ns
Clock LOW period
t
LOW 1.3 – µs
SCL clock frequency
f
SCL – 400 kHz
Data-in setup time
t
SU:DAT 100 – ns
Start condition setup time
t
SU:STA 0.6 – µs 3
Stop condition setup time
t
SU:STO 0.6 – µs
WRITE cycle time
t
WRC – 10 ms 4
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

MT18VDDF12872Y-40BJ1

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Manufacturer:
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Description:
MODULE DDR SDRAM 1GB 184RDIMM
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