AD9203WARUZRL7

10-Bit, 40 MSPS, 3 V, 74 mW
Analog-to-Digital Converter
Automotive Product
AD9203W
Rev. 0
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FEATURES
CMOS 10-bit, 40 MSPS sampling analog-to-digital converter
Power dissipation: 74 mW (3 V supply, 40 MSPS)
17 mW (3 V supply, 5 MSPS)
Operation between 2.7 V and 3.6 V supply
Differential nonlinearity: −0.25 LSB
Power-down (standby) mode: 0.65 mW
ENOB: 9.55 at f
IN
= 20 MHz
Out-of-range indicator
Adjustable on-chip voltage reference
IF undersampling up to f
IN
= 130 MHz
Input range: 1 V to 2 V p-p differential or single-ended
Adjustable power consumption
Internal clamp circuit
Qualified for automotive applications
APPLICATIONS
Automotive
FUNCTIONAL BLOCK DIAGRAM
10258-001
SHA GAIN
A/D D/A
SHA GAIN
A/D D/A
A/D
CORRECTION LOGIC
AD9203W
OUTPUT BUFFERS
10
+
0.5V
BANDGAP
REFERENCE
CLK
A
VDD DRVDD
STBY
3-STATE
OTR
D9 (MSB)
D0 (LSB)
DRVSSDFSPWRCONAVSS
CLAMP
CLAMPIN
AINP
AINN
REFTF
REFBF
VREF
REFSENSE
Figure 1.
GENERAL DESCRIPTION
The AD9203W is a monolithic low power, single supply, 10-bit,
40 MSPS analog-to-digital converter, with an on-chip voltage
reference. The AD9203W uses a multistage differential pipeline
architecture and guarantees no missing codes over the full
operating temperature range. Its input range may be adjusted
between 1 V and 2 V p-p.
The AD9203W has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy
and temperature drift requirements of an application.
An external resistor can be used to reduce power consumption
when operating at lower sampling rates. This yields power
savings for users who do not require the maximum sample
rate. This feature is especially useful at sample rates far below
40 MSPS. Excellent performance is still achieved at reduced
power. For example, 9.7 ENOB performance may be realized
with only 17 mW of power, using a 5 MHz clock.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary or
twos complementary output format by using the DFS pin. An
out-of-range signal (OTR) indicates an overflow condition that
can be used with the most significant bit to determine over- or
underrange.
The AD9203W can operate with a supply range from 2.7 V to
3.6 V, an attractive option for low power operation in high
speed portable applications.
The AD9203W is specified over industrial (−40°C to +85°C)
temperature ranges and is available in a 28-lead TSSOP package.
PRODUCT HIGHLIGHTS
1. Low Power. The AD9203W consumes 74 mW on a 3 V
supply operating at 40 MSPS. In standby mode, power is
reduced to 0.65 mW.
2. High Performance. Maintains better than 9.55 ENOB at
40 MSPS input signal from dc to Nyquist.
3. Ver y Small Package. T he AD9203W is available in a
28-lead TSSOP.
4. Programmable Power. The AD9203W power can be
further reduced by using an external resistor at lower
sample rates.
5. Built-In Clamp Function. Allows dc restoration of video
signals.
AD9203W Automotive Product
Rev. 0 | Page 2 of 8
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Characteristics ...............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions ..............................6
Outline Dimensions ..........................................................................7
Ordering Guide .............................................................................7
REVISION HISTORY
10/11—Revision 0: Initial Version
Automotive Product AD9203W
Rev. 0 | Page 3 of 8
SPECIFICATIONS
AVDD = 3 V, DRVDD = 3 V, F
S
= 40 MSPS, input span from 0.5 V to 2.5 V, internal 1 V reference, PWRCON = AVDD, 50% clock duty
cycle, T
MIN
to T
MAX
unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Conditions
RESOLUTION 10 Bits
MAX CONVERSION RATE F
S
40 MSPS
PIPELINE DELAY 5.5
Clock
Cycles
DC ACCURACY
Differential Nonlinearity DNL ±0.25 ±0.7 LSB
Integral Nonlinearity INL ±0.65 ±1.4 LSB
Offset Error E
ZS
±0.6 ±2.8 % FSR
Gain Error E
FS
±0.7 ±4.0 % FSR
ANALOG INPUT
Input Voltage Range AIN 1 2 V p-p
Input Capacitance C
IN
1.4 pF
Aperture Delay T
AP
2.0 ns
Aperture Uncertainty (Jitter) T
AJ
1.2 ps rms
Input Bandwidth (–3 dB) BW 390 MHz
Input Referred Noise 0.3 mV Switched, single-ended
INTERNAL REFERENCE
Output Voltage (0.5 V Mode) VREF 0.5 V REFSENSE = VREF
Output Voltage (1 V Mode) VREF 1 V REFSENSE = GND
Output Voltage Tolerance (1 V Mode) ± 5 ± 30 mV
Load Regulation 0.65 1.2 mV 1.0 mA load
POWER SUPPLY
Operating Voltage AVDD 2.7 3.0 3.6 V
DRVDD 2.7 3.0 3.6 V
Analog Supply Current IAVDD 20.1 22.0 mA
Digital Supply Current IDRVDD 4.4 6.0 mA f
IN
= 4.8 MHz, output bus load = 10 pF
9.5 14.0 mA f
IN
= 20 MHz, output bus load = 20 pF
Power Consumption 74 84.0 mW f
IN
= 4.8 MHz, output bus load = 10pF
88.8 108.0 mW f
IN
= 20 MHz, output bus load = 20 pF
Power-Down P
D
0.65 1.2 mW
Power Supply Rejection Ratio PSRR 0.04 ± 0.25 % FSR
DYNAMIC PERFORMANCE (AIN = 0.5 dBFS)
Signal-to-Noise and Distortion
1
SINAD
f = 4.8 MHz 59.7 dB
f = 20 MHz 57.2 59.3 dB
Effective Bits ENOB
f = 4.8 MHz
1
9.6 Bits
f = 20 MHz 9.2 9.55 Bits
Signal-to-Noise Ratio SNR
f = 4.8 MHz
1
60.0 dB
f = 20 MHz 57.5 59.5 dB
Total Harmonic Distortion THD
f = 4.8MHz −76.0 dB
f = 20 MHz −74.0 −65.0 dB
Spurious-Free Dynamic Range SFDR
f = 4.8 MHz
1
80 dB
f = 20 MHz 67.8 78 dB

AD9203WARUZRL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10-bit low power 40MSPS ADC
Lifecycle:
New from this manufacturer.
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