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2309-1HDCG

P1-P3P4-P6P7-P9P10-P10
7
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309
3.3V ZERO DELAY CLOCK BUFFER
VDD
OUTPUTS
CLK
OUT
C
LOAD
V
DD
GND GND
0.1
F
0.1
F
VDD
OUTPUTS
10pF
V
DD
GND
GND
0.1
F
0.1
F
1K
1K
CLK
OUT
Output
1.4V
1.4V
t5
Output
REF
VDD/2
t6
Output
CLK
OUT
Device 1
t7
CLK
OUT
Device 2
VDD/2
V
DD/2
V
DD/2
1.4V
1.4V
t2
t1
1.4V
2V
0.8V
t3
t4
0.8V
3.3V
0V
2V
Output
All Outputs Rise/Fall Time
Input to Output Propagation Delay
Device to Device Skew
Output to Output Skew
Duty Cycle Timing
SWITCHING WAVEFORMS
Test Circuit 1 (all Parameters Except t8)
Test Circuit 2 (t8, Output Slew Rate On -1H Devices)
TEST CIRCUITS
8
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309
3.3V ZERO DELAY CLOCK BUFFER
TYPICAL DUTY CYCLE
(1)
AND IDD TRENDS
(2)
FOR IDT2309-1
NOTES:
1. Duty Cycle is taken from typical chip measured at 1.4V.
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F);
V = Supply Voltage (V); f = Frequency (Hz))
3
3.1
3.2
3.3
3.4
3.5 3.6
VDD (V)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs V
DD
(for 30pf loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
D
u
t
y
C
y
c
l
e
(
%
)
3
3.1
3.2
3.3
3.4
3.5 3.6
VDD (V)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs V
DD
(for 10pF loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
20
40
60
80 100 120 140
Frequency (MHz)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs Frequency
(for 30pf loads over temperature - 3.3V)
-40C
0C
25C
70C
85C
D
u
t
y
C
y
c
l
e
(
%
)
D
u
t
y
C
y
c
l
e
(
%
)
133MHz
20
40
60
80 100 120 140
Frequency (MHz)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs Frequency
(for 10pF loads over temperature - 3.3V)
-40C
0C
25C
70C
85C
D
u
t
y
C
y
c
l
e
(
%
)
02
4
6
8
Number of Loaded Outputs
0
20
40
60
80
100
120
140
I
DD vs Number of Loaded Outputs
(for 30pf loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
I
D
D
(
m
A
)
02
4
6
8
Number of Loaded Outputs
0
20
40
60
80
100
120
140
I
DD vs Number of Loaded Outputs
(for 10pF loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
I
D
D
(
m
A
)
9
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2309
3.3V ZERO DELAY CLOCK BUFFER
TYPICAL DUTY CYCLE
(1)
AND IDD TRENDS
(2)
FOR IDT2309-1H
NOTES:
1. Duty Cycle is taken from typical chip measured at 1.4V.
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);
f = Frequency (Hz))
3
3.1
3.2
3.3
3.4
3.5 3.6
VDD (V)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs V
DD
(for 30pf loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
D
u
t
y
C
y
c
l
e
(
%
)
3
3.1
3.2
3.3
3.4
3.5 3.6
VDD (V)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs V
DD
(for 10pF loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
20
40
60
80 100 120 140
Frequency (MHz)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs Frequency
(for 30pf loads over temperature - 3.3V)
-40C
0C
25C
70C
85C
D
u
t
y
C
y
c
l
e
(
%
)
D
u
t
y
C
y
c
l
e
(
%
)
133MHz
20
40
60
80 100 120 140
Frequency (MHz)
40
42
44
46
48
50
52
54
56
58
60
Duty Cycle vs Frequency
(for 10pF loads over temperature - 3.3V)
-40C
0C
25C
70C
85C
D
u
t
y
C
y
c
l
e
(
%
)
02
4
6
8
Number of Loaded Outputs
0
20
40
60
80
100
120
140
I
DD vs Number of Loaded Outputs
(for 30pf loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
I
D
D
(
m
A
)
02
4
6
8
Number of Loaded Outputs
0
20
40
60
80
100
120
140
I
DD vs Number of Loaded Outputs
(for 10pF loads over frequency - 3.3V, 25C)
33MHz
66MHz
100MHz
I
D
D
(
m
A
)
160
160
P1-P3P4-P6P7-P9P10-P10

2309-1HDCG

Mfr. #:
Buy 2309-1HDCG
Manufacturer:
IDT
Description:
Clock Buffer 3.3V PLL ZERO DELAY CLOCK BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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