2309-1HDCGI Datasheet 2309-1DCG8, 2309-1HPGGI8, 2309-1HPGGI | P1-P3

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT2309

3.3V ZERO DELAY CLOCK BUFFER

AUGUST 2012

2012 Integrated Device Technology, Inc. DSC 5175/7c

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five and one bankd

of four outputs

• Separate output enable for each output bank

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• IDT2309-1 for Standard Drive

• IDT2309-1H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Available in SOIC and TSSOP packages

FUNCTIONAL BLOCK DIAGRAM

IDT2309

3.3V ZERO DELAY

CLOCK BUFFER

DESCRIPTION:

The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer,

designed to address high-speed clock distribution applications. The zero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

The IDT2309 is a 16-pin version of the IDT2305. The IDT2309 accepts

one reference input, and drives two banks of four low skew clocks. The

-1H version of this device operates at up to 133MHz frequency and has

higher drive than the -1 device. All parts have on-chip PLLs which lock

to an input clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad. In the absence of an input clock, the

IDT2309 enters power down, and the outputs are tri-stated. In this mode,

the device will draw less than 25µA.

The IDT2309 is characterized for both Industrial and Commercial

operation.

PLL

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Control

Logic

REF

CLKOUT

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT2309

3.3V ZERO DELAY CLOCK BUFFER

PIN CONFIGURATION

SOIC/ TSSOP

TOP VIEW

Symbol Rating Max. Unit

VDD Supply Voltage Range –0.5 to +4.6 V

(2)

Input Voltage Range (REF) –0.5 to +5.5 V

I Input Voltage Range –0.5 to V

(except REF) VDD+0.5

IIK (VI < 0) Input Clamp Current –50 mA

IO (VO = 0 to VDD) Continuous Output Current ±50 mA

VDD or GND Continuous Current ±100 mA

A = 55°C Maximum Power Dissipation 0.7 W

(in still air)

(3)

TSTG Storage Temperature Range –65 to +150 ° C

Operating Commercial Temperature 0 to +70 °C

Temperature Range

Operating Industrial Temperature -40 to +85 °C

Temperature Range

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output

clamp-current ratings are observed.

3. The maximum package power dissipation is calculated using a junction temperature

of 150°C and a board trace length of 750 mils.

NOTES:

1. Weak pull down on all outputs.

2. Weak pull ups on these inputs.

PIN DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

(1)

Pin Name Pin Number Type Functional Description

REF 1 IN Input reference clock, 5 Volt tolerant input

CLKA1

(1)

2 Out Output clock for bank A

CLKA2

(1)

3 Out Output clock for bank A

VDD 4, 13 PWR 3.3V Supply

GND 5, 12 GND Ground

CLKB1

(1)

6 Out Output clock for bank B

CLKB2

(1)

7 Out Output clock for bank B

(2)

8 IN Select input Bit 2

(2)

9 IN Select input Bit 1

CLKB3

(1)

10 Out Output clock for bank B

CLKB4

(1)

11 Out Output clock for bank B

CLKA3

(1)

14 Out Output clock for bank A

CLKA4

(1)

15 Out Output clock for bank A

CLKOUT

(1)

16 Out Output clock, internal feedback on this pin

APPLICATIONS:

• SDRAM

• Telecom

• Datacom

• PC Motherboards/Workstations

• Critical Path Delay Designs

REF

CLKA1

161

CLKA2

GND

CLKB1

CLKOUT

CLKA4

GND

VDD

CLKB2

CLKB3

CLKB4

CLKA3

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT2309

3.3V ZERO DELAY CLOCK BUFFER

DC ELECTRICAL CHARACTERISTICS - COMMERCIAL

Symbol Parameter Conditions Min. Max. Unit

VIL Input LOW Voltage Level — 0.8 V

VIH Input HIGH Voltage Level 2 — V

IIL Input LOW Current VIN = 0V — 50 µA

IIH Input HIGH Current VIN = VDD — 100 µA

VOL Output LOW Voltage Standard Drive IOL = 8mA — 0.4 V

High Drive IOL = 12mA (-1H)

VOH Output HIGH Voltage Standard Drive IOH = -8mA 2.4 — V

High Drive IOH = -12mA (-1H)

IDD_PD Power Down Current REF = 0MHz (S2 = S1 = H) — 12 µA

IDD Supply Current Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND — 32 mA

SWITCHING CHARACTERISTICS (2309-1) - COMMERCIAL

(1,2)

Symbol Parameter Conditions Min. Typ. Max. Unit

t1 Output Frequency 10pF Load 10 — 133 MHz

30pF Load 10 — 100

Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 %

t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns

t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns

t5 Output to Output Skew All outputs equally loaded — — 250 ps

t6A Delay, REF Rising Edge to CLKOUT Rising Edge

(2)

Measured at VDD/2 — 0 ±350 ps

t6B Delay, REF Rising Edge to CLKOUT Rising Edge

(2)

Measured at VDD/2 in PLL bypass mode (IDT2309 only) 1 5 8.7 ns

t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps

tJ Cycle-to-Cycle Jitter Measured at 66.66MHz, loaded outputs — — 200 ps

LOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms

NOTES:

1. REF Input has a threshold voltage of VDD/2.

2. All parameters specified with loaded outputs.

Symbol Parameter Min. Max. Unit

VDD Supply Voltage 3 3.6 V

TA Operating Temperature (Ambient Temperature) 0 70 °C

CL Load Capacitance < 100MHz — 30 pF

Load Capacitance 100MHz - 133MHz — 10

CIN Input Capacitance — 7 pF

OPERATING CONDITIONS - COMMERCIAL

FUNCTION TABLE

(1)

S2 S1 CLKA CLKB CLKOUT

(2)

Output Source PLL Shut Down

L L Tri-State Tri-State Driven PLL N

L H Driven Tri-State Driven PLL N

H L Driven Driven Driven REF Y

H H Driven Driven Driven PLL N

NOTES:

1. H = HIGH Voltage Level.

L = LOW Voltage Level

2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.

P1-P3 P4-P6 P7-P9 P10-P10

2309-1HDCGI

Mfr. #:

Buy 2309-1HDCGI

Manufacturer:

IDT

Description:

Clock Buffer 3.3V PLL ZERO DELAY CLOCK BUFFER

Lifecycle:

New from this manufacturer.

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2309-1HDCGI

2309-1HDCGI

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