AT27LV520
2
Atmel’s innovative design techniques provide fast speeds
that rival 5V parts while keeping the low power consump-
tion of a 3.3V supply. At V
CC
= 3.0V, any byte can be
accessed in less than 70 ns. With a typical power dissipa-
tion of only 18 mW at 5 MHz and V
CC
= 3.3V, the
AT27LV520 consumes less than one fifth the power of a
standard 5V EPROM. Standby mode is achieved by assert-
ing ALE high. Standby mode supply current is typically less
than 1 µA at 3.3V.
The AT27LV520 operating with V
CC
at 3.0V produces TTL
level outputs that are compatible with standard TTL logic
devices operating at V
CC
= 5.0V. The device is also capa-
ble of standard 5-volt operation making it ideally suited for
dual supply range systems or card products that are plug-
gable in both 3-volt and 5-volt hosts.
Atmel’s AT27LV520 has additional features to ensure high
quality and efficient production use. The Rapid
™
Program-
ming Algorithm reduces the time required to program the
part and guarantees reliable programming. Programing
time is typically only 50 µs/byte. The Integrated Product
Identification Code electronically identifies the device and
manufacturer. This feature is used by industry standard
programming equipment to select the proper programming
algorithms and voltages. The AT27LV520 programs exactly
the same way as a standard 5V AT27C520 and uses the
same programming equipment.
System Considerations
Switching under active conditions may produce transient
voltage excursions. Unless accommodated by the system
design, these transients may exceed data sheet limits,
resulting in device non-conformance. At a minimum, a
0.1 µF high frequency, low inherent inductance, ceramic
capacitor should be utilized for each device. This capacitor
should be connected between the V
CC
and Ground termi-
nals of the device, as close to the device as possible. Addi-
tionally, to stabilize the supply voltage level on printed
circuit boards with large EPROM arrays, a 4.7 µF bulk elec-
trolytic capacitor should be utilized, again connected
between the V
CC
and Ground terminals. This capacitor
should be positioned as close as possible to the point
where the power supply is connected to the array.
Block Diagram
OE, ALE, AND
PROGRAM LOGIC
Y DECODER
X DECODER
Y-GATING
CELL MATRIX
IDENTIFICATION
OUTPUT
BUFFERS
VCC
GND
OE/VPP
LATCHES
ALE
AD7 - AD0
A15 - A8
8
8
