LTC3865EUH#TRPBF Datasheet LTC3865EUH-1#PBF, LTC3865IUH#PBF, LTC3865IUH-1#PBF | P25-P27

LTC3865/LTC3865-1

3865fb

APPLICATIONS INFORMATION

If the external clock frequency is greater than the inter-

nal oscillator’s frequency, f

OSC

, then current is sourced

continuously from the phase detector output, pulling up

the ﬁ lter network. When the external clock frequency is

less than f

OSC

, current is sunk continuously, pulling down

the ﬁ lter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. The voltage on the ﬁ lter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the ﬁ lter capacitor holds the voltage.

Typically, the external clock (on MODE/PLLIN pin)

input high threshold is 1.6V, while the input low thres-hold

is 1V. The external clock should not be applied when the

IC is in shutdown.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

, is the smallest time duration

that the LTC3865/LTC3865-1 is capable of turning on the

top MOSFET. It is determined by internal timing delays

and the gate charge required to turn on the top MOSFET.

Low duty cycle applications may approach this minimum

on-time limit and care should be taken to ensure that

ON MIN

OUT

()

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for the LTC3865/LTC3865-1 is

approximately 90ns, with reasonably good PCB layout,

minimum 30% inductor current ripple and at least 10mV

to 15mV ripple on the current sense signal. The mini-

mum on-time can be affected by PCB switching noise in

the voltage and current loop. As the peak sense voltage

decreases the minimum on-time gradually increases to

130ns. This is of particular concern in forced continuous

applications with low ripple current at light loads. If the

duty cycle drops below the minimum on-time limit in this

situation, a signiﬁ cant amount of cycle skipping can occur

with correspondingly larger current and voltage ripple.

Efﬁ ciency Considerations

The percent efﬁ ciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁ ciency and which change would

produce the most improvement. Percent efﬁ ciency can

be expressed as:

%Efﬁ ciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3865/LTC3865-1 circuits: 1) IC V

current,

2) INTV

regulator current, 3) I

R losses, 4) Topside

MOSFET transition losses.

1. The V

current is the DC supply current given in

the Electrical Characteristics table, which excludes

MOSFET driver and control currents. V

current typi-

cally results in a small (<0.1%) loss.

2. INTV

current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

from INTV

to ground. The resulting dQ/dt is a cur-

rent out of INTV

that is typically much larger than the

control circuit current. In continuous mode, I

GATECHG

= f(Q

+ Q

), where Q

and Q

are the gate charges of

the topside and bottom side MOSFETs.

LTC3865/LTC3865-1

3865fb

APPLICATIONS INFORMATION

Supplying INTV

power through EXTV

from an

output-derived source will scale the V

current re-

quired for the driver and control circuits by a factor

of (Duty Cycle)/(Efﬁ ciency). For example, in a 20V

to 5V application, 10mA of INTV

current results in

approximately 2.5mA of V

current. This reduces the

mid-current loss from 10% or more (if the driver was

powered directly from V

) to only a few percent.

3. I

R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resistor.

In continuous mode, the average output current ﬂ ows

through L and R

SENSE

, but is “chopped” between the

topside MOSFET and the synchronous MOSFET. If the

two MOSFETs have approximately the same R

DS(ON)

then the resistance of one MOSFET can simply be

summed with the resistances of L and R

SENSE

to obtain

R losses. For example, if each R

DS(ON)

= 10mΩ, R

10mΩ, R

SENSE

= 5mΩ, then the total resistance is

25mΩ. This results in losses ranging from 2% to 8%

as the output current increases from 3A to 15A for

a 5V output, or a 3% to 12% loss for a 3.3V output.

Efﬁ ciency varies as the inverse square of V

OUT

for the

same external components and output power level. The

combined effects of increasingly lower output voltages

and higher currents required by high performance digital

systems is not doubling but quadrupling the importance

of loss terms in the switching regulator system!

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁ cant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

Transition Loss = (1.7) V

O(MAX)

RSS

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efﬁ ciency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

has adequate charge storage and very low ESR at the

switching frequency. A 25W supply will typically require a

minimum of 20µF to 40µF of capacitance having a max-

imum of 20mΩ to 50mΩ of ESR. The LTC3865 2-phase

architecture typically halves this input capacitance require-

ment over competing solutions. Other losses including

Schottky conduction losses during dead time and induc-

tor core losses generally account for less than 2% total

additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V

OUT

shifts by an

amount equal to ΔI

LOAD

(ESR), where ESR is the effective

series resistance of C

OUT

. ΔI

LOAD

also begins to charge or

discharge C

OUT

generating the feedback error signal that

forces the regulator to adapt to the current change and

return V

OUT

to its steady-state value. During this recovery

time V

OUT

can be monitored for excessive overshoot or

ringing, which would indicate a stability problem. The

availability of the I

pin not only allows optimization of

control loop behavior but also provides a DC coupled and

AC ﬁ ltered closed loop response test point. The DC step,

rise time and settling at this test point truly reﬂ ects the

closed loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining the

rise time at the pin. The I

external components shown

in the Typical Application circuit will provide an adequate

starting point for most applications.

LTC3865/LTC3865-1

3865fb

APPLICATIONS INFORMATION

The I

series R

-C

ﬁ lter sets the dominant pole-zero

loop compensation. The values can be modiﬁ ed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁ nal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1µs to 10µs will

produce output voltage and I

pin waveforms that will

give a sense of the overall loop stability without break-

ing the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

is why it is better to look at the I

pin signal which is in

the feedback loop and is the ﬁ ltered and compensated

control loop response. The gain of the loop will be in-

creased by increasing R

and the bandwidth of the loop

will be increased by decreasing C

. If R

is increased by

the same factor that C

is decreased, the zero frequency

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with C

OUT

, causing a rapid drop in V

OUT

. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

LOAD

to C

OUT

is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately 25 • C

LOAD

. Thus a 10µF capacitor would

require a 250µs rise time, limiting the charging current

to about 200mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 12. Figure 13 illustrates the

current waveforms present in the various branches of

the 2-phase synchronous regulators operating in the

continuous mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 located

within 1 cm of each other with a common drain con-

nection at C

? Do not attempt to split the input de-

coupling for the two channels as it can cause a large

resonant loop.

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

of C

INTVCC

must return to the combined C

OUT

(–) ter-

minals. The V

OSENSE

and I

traces should be as short

as possible. The path formed by the top N-channel

MOSFET, Schottky diode and the C

capacitor should

have short leads and PC trace lengths. The output

capacitor (–) terminals should be connected as close

as possible to the (–) terminals of the input capacitor

by placing the capacitors next to each other and away

from the Schottky loop described above.

3. Do the LTC3865 V

OSENSE

pins connect to the (+) terminals

of C

OUT

? The connections between the V

OSENSE

pins

and C

OUT

should not be along the high current input

feeds from the input capacitor(s).

4. Are the SENSE

and SENSE

–

leads routed together with

minimum PC trace spacing? The ﬁ lter capacitor between

SENSE

and SENSE

–

should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the sense resistor or inductor, whichever

is used for current sensing.

5. Is the INTV

decoupling capacitor connected close to

the IC, between the INTV

and the power ground pins?

This capacitor carries the MOSFET drivers current peaks.

An additional 1µF ceramic capacitor placed immediately

next to the INTV

and PGND pins can help improve

noise performance substantially.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P38

LTC3865EUH#TRPBF

Mfr. #:

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Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators Dual, 2-Phase Synchronous DC/DC Controller with Pin Selectable Outputs

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