LTC3634
8
3634fc
For more information www.linear.com/LTC3034
PIN FUNCTIONS
PGOOD1 (Pin 1/Pin 4): Channel 1 Open-Drain Power Good
Output Pin. PGOOD1 is pulled to ground when the voltage
on the V
FB1
pin is not within ±8% (typical) of the internal
0.6V reference. This threshold has 15mV of hysteresis.
PHMODE (Pin 2/Pin 5): Phase Select Input. Tie this pin to
ground to force both channels to switch 90° out-of-phase.
Tie this pin to INTV
CC
to force both channels to switch
180° out-of-phase. Do not float this pin.
RUN1 (Pin 3/Pin 6): Channel 1 Regulator Enable Pin.
Enables channel 1 operation by tying RUN1 above 1.22V.
Tying it below 1V places Channel 1 into shutdown. Do not
float this pin.
MODE/SYNC (Pin 4/Pin 7): Channel 1 Mode Select and
External Synchronization Input. Tie this pin to ground to
force continuous synchronous operation on Channel 1.
Floating this pin or tying it to INTV
CC
enables high
efficiency Burst Mode
®
operation at light loads. Channel 2
operation is forced continuous regardless of the state of
this pin. Drive this pin with a clock to synchronize the
LTC3634 switching frequency. An internal phase-locked
loop will force the bottom power NMOS’s turn-on signal to
be synchronized with the rising edge of the CLKIN signal.
When this pin is driven with a clock, forced continuous
mode is automatically selected.
RT (Pin 5/Pin 8): Oscillator Frequency Program Pin.
Connect an external resistor (between 80k to 640k) from
this pin to SGND in order to program the frequency from
500kHz to 4MHz. When RT is tied to INTV
CC
, the switch-
ing frequency will default to 2MHz. See the Applications
Information section.
RUN2 (Pin 6/Pin 9): Channel 2 Regulator Enable Pin.
Enables channel 2 operation by tying RUN2 above 1.22V.
Tying it below 1V places Channel 2 into shutdown. Do not
float this pin.
SGND (Pin 7/Pin 10): Signal Ground Pin. This pin should
have a low noise connection to reference ground. The
feedback resistor network, external compensation network,
and R
T
resistor should be connected to this ground.
PGOOD2 (Pin 8/Pin 11): Channel 2 Open-Drain Power
Good Output Pin. PGOOD2 is pulled to ground when
the voltage on the V
FB2
pin is not within 8% (typical) of
VDDQIN • 0.5. This threshold has 15mV of hysteresis.
V
FB2
(Pin 9/Pin 12): Channel 2 Output Feedback Voltage
Pin. Input to the error amplifier that compares the feedback
voltage to VTTR. Connect this pin directly to the output in
order to set V
OUT2
equal to VTTR.
VDDQIN (Pin 10/Pin 13): External Reference Input for
Channel 2. An internal resistor divider sets the VTTR pin
voltage to be equal to half the voltage applied to this input.
Channel 2 uses the VTTR pin voltage as its error amplifier
reference.
ITH2 (Pin 11/Pin 14): Channel 2 Error Amplifier Output
and Switching Regulator Compensation Pin. Connect this
pin to appropriate external components to compensate the
regulator loop frequency response. See the Applications
Information section for guidelines on component selection.
V
ON2
(Pin 12/Pin 15): On-Time Voltage Input for Chan-
nel 2. This pin sets the voltage trip point for the on-time
comparator. Tying this pin to the output voltage makes the
on-time proportional to V
OUT2
when V
OUT2
< 3V. When
V
OUT2
> 3V, switching frequency may become higher than
the set frequency (see the Applications Information sec-
tion). The pin impedance is nominally 150kΩ.
SW2 (Pins 13, 14/Pins 16, 17): Channel 2 Switch Node
Connection to External Inductor. Voltage swing of SW is
from a diode voltage below ground to a diode voltage
above V
IN2
.
V
IN2
(Pins 15, 16/Pins 18, 19): Power Supply Input for
Channel 2. Input voltage to the on-chip power MOSFETs
on channel 2. This input is capable of operating from a
supply voltage separate from V
IN1
.
BOOST2 (Pin 17/Pin 20): Boosted Floating Driver Supply
for Channel 2. The (+) terminal of the bootstrap capacitor
connects to this pin while the (–) terminal connects to
the SW pin. The normal operation voltage swing of this
pin ranges from a diode voltage drop below INTV
CC
up
to V
IN2
+ INTV
CC
.
(QFN/TSSOP)
