LTC3634
21
3634fc
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1. Conduction losses are calculated from the DC resis-
tances of the internal switches, R
SW
, and external
inductor, R
L
. In continuous mode, the average output
current flows through inductor L but is “chopped”
between the internal top and bottom power MOSFETs.
Thus, the series resistance looking into the SW pin is a
function of both top and bottom MOSFET R
DS(ON)
and
the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. So to calculate conduction losses:
Conduction Loss = I
OUT
2
(R
SW
+ R
L
)
2. The internal LDO supplies the power to the INTV
CC
rail.
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from
V
IN
to ground. The resulting dQ/dt is a current out of
INTV
CC
that is typically much larger than the DC control
bias current. In continuous mode, I
GATECHG
= f • (Q
T
+
Q
B
), where Q
T
and Q
B
are the gate charges of the internal
top and bottom power MOSFETs and f is the switching
frequency. For estimation purposes, (Q
T
+ Q
B
) on each
LTC3634 regulator channel is approximately 2.3nC.
To calculate the total power loss from the LDO load,
simply add the gate charge current and quiescent cur-
rent and multiply by V
IN
:
P
LDO
= (I
GATECHG
+ I
Q
) • V
IN
3. Other hidden losses such as transition loss, copper trace
resistances, and internal load currents can account for
additional efficiency degradations in the overall power
system. Transition loss arises from the brief amount of
time the top power MOSFET spends in the saturated
region during switch node transitions. The LTC3634
internal power devices switch quickly enough that these
losses are not significant compared to other sources.
Other losses, including diode conduction losses during
dead-time and inductor core losses, generally account
for less than 2% total additional loss.
Thermal Considerations
The LTC3634 requires the exposed package back-plane
metal (PGND) to be well soldered to the PC board to
provide good thermal contact. This gives the QFN and
TSSOP packages exceptional thermal properties, which
are necessary to prevent excessive self-heating of the part
in normal operation.
In a majority of applications, the LTC3634 does not dis-
sipate much heat due to its high efficiency and low thermal
resistance of its exposed-back QFN package. However, in
applications where the LTC3634 is running at high ambi-
ent temperature, high V
IN
, high switching frequency, and
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 170°C,
both power switches will be turned off until the temperature
returns to 160°C.
To prevent the LTC3634 from exceeding the maximum
junction temperature of 125°C, the user will need to do
some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
RISE
= P
D
• θ
JA
As an example, consider the case when the LTC3634 is
used to power DDR2 SDRAM and is used in an application
where maximum ambient temperature is 70°C, V
IN
= 12V,
frequency = 1MHz, V
DDQ
= 1.8V, V
TT
= 0.9V, and I
LOAD
=
2A for both channels.
From the R
DS(ON)
graphs in the Typical Performance
Characteristics section, the top switch on-resistance is
nominally 140mΩ and the bottom switch on-resistance
is nominally 75mΩ at 70°C ambient. For the V
DDQ
supply,
the equivalent power MOSFET resistance R
SW1
is:
R
DS(ON)TOP
•
+R
DS(ON)BOT
•
= 84.8mΩ
The same calculation to the V
TT
supply (0.9V), yields
R
SW2
= 79.9mΩ.
From the previous section’s discussion on gate drive, we
estimate the total gate charge current for each regulator to
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