conversion result). (See Figure 16 for MAX1282/
MAX1283 QSPI connections.)
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 500kHz to 6.4MHz (MAX1282) or
4.8MHz (MAX1283).
1) Set up the control byte and call it TB1. TB1 should
be in the format: 1XXXXXXX binary, where the Xs
denote the particular channel, selected conversion
mode, and power mode.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 5 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with three leading zeros, and one trailing zero. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 13). For bipolar input mode, the output is two’s
complement (Figure 14). Data is clocked out on the ris-
ing edge of SCLK in MSB-first format.
Serial Clock
The external clock not only shifts data in and out, but it
also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the
next 12 SCLK rising edges, MSB first (Figure 5). SSTRB
and DOUT go into a high-impedance state when CS
goes high; after the next CS falling edge, SSTRB out-
puts a logic low. Figure 6 shows the detailed serial-inter-
face timings.
The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
Data Framing
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after V
DD1
and V
DD2
are applied.
or
The first high bit clocked into DIN after B6 of a con-
version in progress is clocked onto the DOUT pin
(Figure 7).
Once a start bit has been recognized, the current conver-
sion may only be terminated by pulling SHDN low.
The fastest the MAX1282/MAX1283 can run with CS held
low between conversions is 16 clocks per conversion.
Figure 7 shows the serial-interface timing necessary to
perform a conversion every 16 SCLK cycles. If CS is tied
low and SCLK is continuous, guarantee a start bit by first
clocking in 16 zeros.
___________Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1282/MAX1283 in normal operating mode, ready to
convert with SSTRB = low. After the power supplies sta-
bilize, the internal reset time is 10µs, and no conver-
sions should be performed during this phase. If CS is
low, the first logic 1 on DIN is interpreted as a start bit.
Until a conversion takes place, DOUT shifts out zeros.
Additionally, wait for the reference to stabilize when
using the internal reference.
Power Modes
Save power by placing the converter in one of two low-
current operating modes or in full power-down between
conversions. Select the power-down mode through bit
1 and bit 0 of the DIN control byte (Tables 3 and 4), or
force the converter into hardware shutdown by driving
SHDN to GND.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
progress. In software power-down mode, the serial
interface remains active while waiting for a new control
byte to start conversion and switch to full-power mode.
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
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