MAX544/MAX545
+5V, Serial-Input, Voltage-Output, 14-Bit DACs
_______________________________________________________________________________________ 7
Detailed Description
The MAX544/MAX545 voltage-output, 14-bit digital-to-
analog converters (DACs) offer full 14-bit performance
with less than 0.5LSB integral linearity error and less
than 0.9LSB differential linearity error, thus ensuring
monotonic performance. Serial-data transfer minimizes
the number of package pins required.
The MAX544/MAX545 are composed of two matched
DAC sections, with an inverted R-2R DAC forming the
LSBs and the four MSBs derived from 15 identically
matched resistors. This architecture allows the lowest
glitch energy to be transferred to the DAC output on
major-carry transitions. It also lowers the DAC output
impedance by a factor of eight compared to a standard
R-2R ladder, allowing unbuffered operation in medium-
load applications.
The MAX545 provides matched bipolar offset resistors,
which connect to an external op amp for bipolar output
swings (Figure 2b). For optimum performance, the
MAX545 also provides a set of Kelvin connections to
the voltage-reference and analog-ground inputs.
MAX545
MAX400
AGNDFDGND
(GND)
V
DD
REFF
REFS
R
INV
R
FB
RFB
INV
OUT
LDAC
SCLK
DIN
CS
AGNDS
0.1µF
+5V
EXTERNAL OP AMP
MC68XXXX
PCS0
MOSI
SCLK
IC1
BIPOLAR
OUT
+5V
-5V
0.1µF
+2.5V
10µF
Figure 2b. Typical Operating Circuit—Bipolar Output
MAX544/MAX545
MAX495
DGND
( ) ARE FOR MAX545 ONLY
(GND)
V
DD
(REFS)REF (REFF)
OUT
SCLK
DIN
CS
AGND_
0.1µF
0.1µF
+5V
+2.5V
EXTERNAL OP AMP
MC68XXXX
PCS0
MOSI
SCLK
UNIPOLAR
OUT
(LDAC)
10µF
Figure 2a. Typical Operating Circuit—Unipolar Output
MAX544/MAX545
+5V, Serial-Input, Voltage-Output, 14-Bit DACs
8 _______________________________________________________________________________________
Digital Interface
The MAX544/MAX545’s digital interface is a standard
3-wire connection compatible with SPI/QSPI/
MICROWIRE interfaces. The chip-select input (CS)
frames the serial data loading at the data-input pin
(DIN). Immediately following CS’s high-to-low transition,
the data is shifted synchronously and latched into the
input register on the rising edge of the serial clock input
(SCLK). After 16 bits (14 data bits, plus 2 sub-bits set to
zero) have been loaded into the serial input register, it
transfers its contents to the DAC latch on CS’s low-to-
high transition (Figure 3a). Note that if CS is not kept
low during the entire 16 SCLK cycles, data will be cor-
rupted. In this case, reload the DAC latch with a new
16-bit word.
Alternatively, for the MAX545, LDAC allows the DAC
latch to update asynchronously by pulling LDAC low
after CS goes high (Figure 3b). Hold LDAC high during
the data-loading sequence.
External Reference
The MAX544/MAX545 operate with external voltage ref-
erences from 2V to 3V. The reference voltage deter-
mines the DAC’s full-scale output voltage. Kelvin
connections are provided with the MAX545 for optimum
performance. The 2.5V MAX873A, with ±15mV initial
accuracy and a 7ppm/°C (max) temperature coeffi-
cient, is a good choice.
Power-On Reset
The MAX544/MAX545 have a power-on reset circuit to
set the DAC’s output to 0V in unipolar mode when V
DD
is first applied. This ensures that unwanted DAC output
voltages will not occur immediately following a system
power-up, such as after a loss of power. In bipolar
mode, the DAC output is set to -V
REF
.
CS
SCLK
DIN
MSB LSB
D13 D6 D5 D4 D3 D2 D1 D0 S1 S0
SUB-BITS
DAC
UPDATED
D12 D11 D10 D9 D8 D7
CS
SCLK
DIN
LDAC
MSB
LSB
D13
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1
S0
DAC
UPDATED
SUB-BITS
Figure 3a. MAX544/MAX545 3-Wire Interface Timing Diagram (
LDAC
= DGND for MAX545)
Figure 3b. MAX545 4-Wire Interface Timing Diagram
MAX544/MAX545
+5V, Serial-Input, Voltage-Output, 14-Bit DACs
_______________________________________________________________________________________ 9
Applications Information
Reference and Analog Ground Inputs
The MAX544/MAX545 operate with external voltage ref-
erences from 2V to 3V, and maintain 14-bit performance
if certain guidelines are followed when selecting and
applying the reference. Ideally, the reference’s
temperature coefficient should be less than 1.5ppm/°C to
maintain 14-bit accuracy to within 1LSB over the 0°C to
+70°C commercial temperature range. Since this convert-
er is designed as an inverted R-2R voltage-mode DAC,
the input resistance seen by the voltage reference is code
dependent. The worst-case input-resistance variation is
from 11.5k (at code 8554 hex) to 200k (at code 0000
hex). The maximum change in load current for a +2.5V
reference is +2.5V / 11.5k = 217µA; therefore, the
required load regulation is 28ppm/mA for a maximum
error of 0.1LSB. This implies a reference output imped-
ance of less than 71m. In addition, the signal-path
impedance from the voltage reference to the reference
input must be kept low because it contributes directly to
the load-regulation error.
The requirement for a low-impedance voltage reference
is met with capacitor bypassing at the reference inputs
and ground. A 0.1µF ceramic capacitor with short leads
between REFF and AGNDF (MAX545), or REF and
AGND (MAX544), provides high-frequency bypassing.
A surface-mount ceramic chip capacitor is preferred
because it has the lowest inductance. An additional
10µF between REFF and AGNDF (MAX545), or REF
and AGND (MAX544), provides low-frequency bypass-
ing. A low-ESR tantalum, film, or organic semiconductor
capacitor works well. Leaded capacitors are accept-
able because impedance is not as critical at lower fre-
quencies. The circuit can benefit from even larger
bypassing capacitors, depending on the stability of the
external reference with capacitive loading. If separate
force and sense lines are not used, tie the appropriate
force and sense pins together close to the package.
AGND must also be low impedance, as load-regulation
errors will be introduced by excessive AGND resis-
tance. As in all high-resolution, high-accuracy applica-
tions, separate analog and digital ground planes yield
the best results. Tie DGND to AGND at the AGND pin to
form the “star” ground for the DAC system. Always refer
remote DAC loads to this system ground for the best
possible performance.
Unbuffered Operation
Unbuffered operation reduces power consumption as
well as offset error contributed by the external output
buffer. The R-2R DAC output is available directly at
OUT, allowing 14-bit performance from +V
REF
to AGND
without degradation at zero scale. The DAC’s output
impedance is also low enough to drive medium loads
(R
L
> 60k) without degradation of INL or DNL; only
the gain error is increased by externally loading the
DAC output.
External Output Buffer Amplifier
The requirements on the external output buffer amplifier
change whether the DAC is used in unipolar or bipolar
operational mode. In unipolar mode, the output amplifi-
er is used in a voltage-follower connection. In bipolar
mode (MAX545 only), the amplifier operates with the
internal scaling resistors (Figure 2b). In each mode, the
DAC’s output resistance is constant and is independent
of input code; however, the output amplifier’s input
impedance should still be as high as possible to mini-
mize gain errors. The DAC’s output capacitance is also
independent of input code, thus simplifying stability
requirements on the external amplifier.
In bipolar mode, a precision amplifier operating with
dual power supplies (such as the MAX400) provides
the ±V
REF
output range. In single-supply applications,
precision amplifiers with input common-mode ranges
including AGND are available; however, their output
swings do not normally include the negative rail
(AGND) without significant degradation of performance.
A single-supply op amp, such as the MAX495, is suit-
able if the application does not use codes near zero.
Since the LSBs for a 14-bit DAC are extremely small
(152.6µV for V
REF
= 2.5V), pay close attention to the
external amplifier’s input specification. The input offset
voltage can degrade the zero-scale error and might
require an output offset trim to maintain full accuracy if
the offset voltage is greater than 1/2LSB. Similarly, the
input bias current multiplied by the DAC output resis-
tance (typically 6.25k) contributes to zero-scale error.
Temperature effects also must be taken into considera-
tion. Over the 0°C to +70°C commercial temperature
range, the offset voltage temperature coefficient (refer-
enced to +25°C) must be less than 1.7µV/°C to add
less than 1/2LSB of zero-scale error. The external

MAX544BCPA+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 14-Bit Precision DAC
Lifecycle:
New from this manufacturer.
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