AD9280ARSZRL Datasheet AD9280ARSZ, AD9280ARSZRL, AD9280ARS | P7-P9

AD9280

–6–

DEFINITIONS OF SPECIFICATIONS

Integral Nonlinearity (INL)

Integral nonlinearity refers to the deviation of each individual

code from a line drawn from “zero” through “full scale.” The

point used as “zero” occurs 1/2 LSB before the first code transi-

tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last

code transition. The deviation is measured from the center of

each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. It is often

specified in terms of the resolution for which no missing codes

(NMC) are guaranteed.

Typical Characterization Curves

CODE OFFSET

1.0

0.5

–1.0

0 24032

DNL

64 96 128 160 192 224

–0.5

Figure 3. Typical DNL

CODE OFFSET

1.0

INL

0.5

–1.0

0 24032 64 96 128 160 192 224

–0.5

Figure 4. Typical INL

Offset Error

The first transition should occur at a level 1 LSB above “zero.”

Offset is defined as the deviation of the actual first code transi-

tion from that point.

Gain Error

The first code transition should occur for an analog value 1 LSB

above nominal negative full scale. The last transition should

occur for an analog value 1 LSB below the nominal positive full

scale. Gain error is the deviation of the actual difference be-

tween first and last code transitions and the ideal difference

between the first and last code transitions.

Pipeline Delay (Latency)

The number of clock cycles between conversion initiation and

the associated output data being made available. New output

data is provided every rising edge.

INPUT FREQUENCY – Hz

1.00E+05 1.00E+081.00E+06 1.00E+07

SNR– dB

–0.5 AMPLITUDE

–6.0 AMPLITUDE

–20.0 AMPLITUDE

Figure 5. SNR vs. Input Frequency

1.00E+05 1.00E+081.00E+06

SINAD – dB

1.00E+07

INPUT FREQUENCY – Hz

–0.5 AMPLITUDE

–6.0 AMPLITUDE

–20.0 AMPLITUDE

Figure 6. SINAD vs. Input Frequency

(AVDD = +3 V, DRVDD = +3 V, F

= 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input

Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)

REV. E

AD9280

–7–

–30

–35

1.00E+05 1.00E+081.00E+06 1.00E+07

–40

–45

–60

–65

THD – dB

–70

INPUT FREQUENCY – Hz

–50

–55

–20.0 AMPLITUDE

–6.0 AMPLITUDE

–0.5 AMPLITUDE

Figure 7. THD vs. Input Frequency

CLOCK FREQUENCY – Hz

–70

–60

1.00E+06 1.00E+081.00E+07

THD – dB

–50

–40

–10

–30

–20

–80

AIN = –0.5dBFS

Figure 8. THD vs. Clock Frequency

TEMPERATURE – °C

1.01

1.009

1.005

–50 90–30

REF

– V

–10

1.008

1.007

1.006

10 30 50 70

CLOCK = 32MHz

Figure 9. Voltage Reference Error vs. Temperature

CLOCK FREQUENCY – MHz

105

100

0405

POWER CONSUMPTION – mW

15 20 25 30 35

Figure 10. Power Consumption vs. Clock Frequency

(MODE = AVSS)

900k

N–1 N

HITS

N+1

800k

700k

100k

400k

300k

200k

CODE

600k

500k

Figure 11. Grounded Input Histogram

SINGLE-TONE FREQUENCY DOMAIN

0E+0 4E+6 8E+6

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

12E+6 16E+6

= 1MHz

= 32MHz

FUND

2nd

3rd

5th

6th

4th

7th

8th

9th

Figure 12. Single-Tone Frequency Domain

REV. E

AD9280

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Table I. Mode Selection

Input Input MODE REFSENSE

Modes Connect Span Pin Pin REF REFTS REFBS Figure

TOP/BOTTOM AIN 1 V AVDD Short REFSENSE, REFTS and VREF Together AGND 18

AIN 2 V AVDD AGND Short REFTS and VREF Together AGND 19

CENTER SPAN AIN 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20

AIN 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2

Differential AIN Is Input 1 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29

REFTS and

REFBS Are

Shorted Together

for Input 2 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2

External Ref AIN 2 V max AVDD AVDD No Connect Span = REFTS 21, 22

– REFBS (2 V max)

AGND Short to Short to 23

VREFTF VREFBF

AD876-8 AIN 2 V Float or AVDD No Connect Short to Short to 30

AVSS VREFTF VREFBF

–9

1.0E+6 1.0E+91.0E+7

SIGNAL AMPLITUDE – dB

1.0E+8

–3

–6

FREQUENCY – Hz

–12

–15

–18

–21

–24

Figure 13. Full Power Bandwidth

–50

0 3.01.0 2.0

–10

–20

–30

INPUT VOLTAGE – V

–40

2.50.5 1.5

– mA

REFBS = 0.5V

REFTS = 2.5V

CLOCK = 32MHz

Figure 14. Input Bias Current vs. Input Voltage

APPLYING THE AD9280

THEORY OF OPERATION

The AD9280 implements a pipelined multistage architecture to

achieve high sample rate with low power. The AD9280 distrib-

utes the conversion over several smaller A/D subblocks, refining

the conversion with progressively higher accuracy as it passes

the results from stage to stage. As a consequence of the distrib-

uted conversion, the AD9280 requires a small fraction of the

256 comparators used in a traditional flash type A/D. A sample-

and-hold function within each of the stages permits the first

stage to operate on a new input sample while the second, third

and fourth stages operate on the three preceding samples.

OPERATIONAL MODES

The AD9280 is designed to allow optimal performance in a

wide variety of imaging, communications and instrumentation

applications, including pin compatibility with the AD876-8 A/D.

To realize this flexibility, internal switches on the AD9280 are

used to reconfigure the circuit into different modes. These modes

are selected by appropriate pin strapping. There are three parts

of the circuit affected by this modality: the voltage reference, the

reference buffer, and the analog input. The nature of the appli-

cation will determine which mode is appropriate: the descrip-

tions in the following sections, as well as Table I should assist in

selecting the desired mode.

REV. E

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AD9280ARSZRL

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Analog to Digital Converters - ADC 8B Complete 32 MSPS

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AD9280ARSZRL

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