1
High Speed, Dual Channel, 6A, MOSFET Driver With
Programmable Rising and Falling Edge Delay Timers
ISL89367
The ISL89367 is a high-speed, 6A, 2 channel MOSFET driver
optimized for synchronous rectifier applications. Internal timers
can be programmed with resistors to delay the rising and/or
falling edges of the outputs. Logically ANDed dual inputs are also
provided. One input is for the PWM signal and the second can be
used as an enable. A third control input is used to optionally
invert the logical polarity of the driver outputs.
Comparator like logical inputs allows this driver to be configured
for any logic level from 3.3V to 10 VDC. The precision logic
thresholds provided by the comparators allow the use of external
RC circuits to generate longer time delays than are possible with
the internal timers. The comparators also allow the driver to be
configured with a low output voltage that is negative relative to
the logic ground if desired. This is useful for applications that
require a negative turn-off gate drive voltage for driving FETs with
logic thresholds.
At high switching frequencies, these MOSFET drivers use very
little bias current. Separate, non-overlapping drive circuits are
used to drive each CMOS output FET to prevent shoot-thru
currents in the output stage.
The start-up sequence is design to prevent unexpected glitches
when V
DD
is being turned on or turned off. When V
DD
< ~1V, an
internal 10kΩ resistor between the output and ground helps to
keep the output voltage low. When ~1V < V
DD
< UV, both outputs
are driven low with very low resistance and the logic inputs are
ignored. This insures that the driven FETs are off. When
V
DD
> UVLO, and after a short delay, the outputs now respond to
the logic inputs.
Features
2 outputs with 6A peak drive currents (sink and source) with
output voltage range of 4.5V to 16V
•Typical ON-resistance <1Ω
Specified Miller plateau drive currents
EPAD provides very low thermal impedance (
JC
= 3°C/W)
Dual logic inputs with hysteresis for high noise immunity
Rising and/or falling output edge delays programmed with
resistors
20ns rise and fall time driving a 10nF load
Flexible logic options available by use of INVA and INVB pins
Applications
Synchronous Rectifier (SR) Driver
Switch mode power supplies
Motor Drives, Class D amplifiers, UPS, Inverters
Pulse Transformer Driver
Clock/Line Driver
Related Literature
AN1603 “ISL6752/54EVAL1Z ZVS DC/DC Power Supply with
Synchronous Rectifiers User Guide”
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. PROGRAMMABLE TIME DELAYS
3.3V
ENABLE
INVA
INVB
PWM
OUTB
/OUTA
VREF+
VREF-
RDELA
RDELB
FDELB
FDELA
GND
12V
0
50
100
150
200
250
300
350
0 5 10 15 20
RISING OR FALLING EDGE DELAY (ns)
RDT (2k TO 20k)
-40°C (WORST CASE)
+125°C (WORST CASE)
+25°C (TYPICAL)
October 8, 2012
FN7727.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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| Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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ISL89367
2
FN7727.1
October 8, 2012
Block Diagram
The positive threshold is
63% of ((VREF+)-(VREF-)).
The negative threshold is
37% of ((VREF+)-(VREF-)).
Delay
Timer
OUTx
VDD
IN1x
INVx
VREF+
VSSVREF-
RDELx
FDELx
IN2x
For clarity, only one
channel is shown
Delay
Timer
Rising edge
is delayed
Falling edge
is delayed
EPAD
Separated gate drives
prevent shoot-thru currents
in the output CMOS FETs.
10K
For proper thermal and
electrical performance, the
EPAD must be connected to
the PCB signal ground plane.
ISL89367
3
FN7727.1
October 8, 2012
Pin Configurations
ISL89367
(16 LD TDFN, EPSOIC)
TOP VIEW
EPAD
INVA
IN1A
INVB
IN2B
IN1B
IN2A
FDELB
RDELB
VSS
OUTB
OUTA
VDD
RDELA
FDELA
1
2
3
4
5
6
7
8
12
9
10
11
13
14
15
16
VREF+
VREF-
INVx IN1x IN2x OUTx
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
OUTx
IN1x
IN2x
INVx
TRUTH TABLE
Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
1, 8 VREF+
VREF-
VREF+ and VREF- are the reference voltages for
the IN1A, IN1B, IN2A, and IN2B logic inputs.
VREF+ is normally connected to the positive bias
voltage of the input logic. VREF- is normally
connected to the ground reference of the input
logic.
2, 7 INVA or
INVB
Connect these pins to VDD to invert the
corresponding output. Connect to VSS to not
invert the corresponding output.
3, 4,
5, 6
IN1A,
IN2A,
IN1B,
IN2B
ANDed logical inputs. One input to each channel
can be used as an enable. Logic high threshold is
63% of [(VREF+) - (VREF-)]. Logic low threshold is
37% of [(VREF+) - (VREF-)].
9, 16 FDELB,
FDELA
Connect a resistor between these pins and VSS to
program the duration of the falling edge
propagation delay of the corresponding output
relative to the logic inputs.
10, 15 RDELB,
RDELA
Connect a resistor between these pins and VSS to
program the duration of the rising edge
propagation delay of the corresponding output
relative to the logic inputs.
11, 14 VSS, VDD Output bias voltage. (VDD to VSS) range is 4.5V to
16V. VSS may be negative relative to VREF-.
12, 13 OUTB,
OUTA
6A peak outputs. Output voltage swing is
between VDD and VSS.
EPAD Must be connected to logic ground (VREF-).
Ordering Information
PART NUMBER
(Notes 1, 2, 3) PART MARKING
TEMP RANGE
(°C) INPUT CONFIGURATION
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL89367FRTAZ 9367A -40 to +125 Non-inverting 16 Ld 3x5 TDFN L16.5x3
NOTES:
1. Add “-T”, suffix for tape and reel. Please refer to TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL89367.
For more information on MSL, please see Technical Brief
TB363
.

ISL89367FRTAZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 6A PEAK HI SPD PWR MSFT DRVR 16LD 5X3
Lifecycle:
New from this manufacturer.
Delivery:
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