© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 1
1
Publication Order Number:
NB6L572M/D
NB6L572M
2.5V / 3.3V Differential 4:1
Mux to 1:2 CML Clock/Data
Fanout / Translator
Multi−Level Inputs w/ Internal Termination
Description
The NB6L572M is a high performance differential 4:1 Clock / Data
input multiplexer and a 1:2 CML Clock / Data fanout buffer that
operates up to 6 GHz / 8 Gbps respectively with a 2.5 V or 3.3 V
power supply.
The differential Clock / Data inputs have internal 50 W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB6L572M incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
CML output copies of Clock or Data.
As such, the NB6L572M is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications.
The two differential CML outputs will swing 400 mV when
externally loaded and terminated with a 50 W resistor to V
CC
and are
optimized for low skew and minimal jitter.
The NB6L572M is offered in a low profile 5x5mm 32−pin QFN
Pb−Free package. Application notes, models, and support
documentation are available at www.onsemi.com. The NB6L572M is
a member of the ECLinPS MAX™ family of high performance clock
products.
Features
• Input Data Rate > 8 Gb/s Typical
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 6 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:2 CML Outputs, < 15 ps max
• 4:1 Multi−Level Mux Inputs, accepts LVPECL, CML
LVDS
• 200 ps Typical Propagation Delay
• 35 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Peak−to−Peak,
Typical
• Operating Range: V
CC
= 2.375 V to 3.6 V with
GND = 0 V
• Internal 50 W Input Termination Resistors
• V
REFAC
Reference Output
• QFN−32 Package, 5mm x 5mm
• 40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 8 of
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
http://onsemi.com
32
1
NB6L
572M
AWLYYWWG
G
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
