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ICS853P022AMLFT

P1-P3P4-P6P7-P9P10-P11
853P022AG www.icst.com/products/hiperclocks.html REV. A FEBRUARY 23, 2005
4
Integrated
Circuit
Systems, Inc.
ICS853P022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
TABLE 2D. ECL DC CHARACTERISTICS, V
CC
= 0V; V
EE
= -3.8V TO -3.0V
lobmySretemaraP
C°04-C°52C°58
stinU
niMpyTxaMniMpyTxaMniMpyTxaM
V
HO
1ETON;egatloVhgiHtuptuO
521.1-520.1-29.0-570.1-500.1-39.0-500.1-79.0-539.0-
V
V
LO
1ETON;egatloVwoLtuptuO
598.1-557.1-26.1-578.1-87.1-586.1-68.1-567.1-76.1-
V
05htiwdetanimretstuptuO:1ETON Ω Vot
CC
.V2-
TABLE 3. AC CHARACTERISTICS, V
CC
= 0V; V
EE
= -3.8V TO -3.0V OR V
CC
= 3.0V TO 3.8V; V
EE
= 0V
lobmySretemaraP
C°04-C°52C°58
stinU
niMpyTxaMniMpyTxaMniMpyTxaM
f
XAM
ycneuqerFtuptuO1.11.11.1zHG
pt
HL
;hgiHotwoL,yaleDnoitagaporP
1ETON
521023006081023574091003014sp
pt
LH
;woLothgiH,yaleDnoitagaporP
1ETON
521023006081023574091003014sp
t
)o(ks4,2ETON;wekStuptuO215521052105sp
t
)pp(ks4,3ETON;wekStraP-ot-traP033522522sp
t
tij
;SMR,rettiJesahPevitiddAreffuB
noitcesrettiJesahPevitiddAotrefer
30.030.030.0sp
t
R
/t
F
emiTllaF/esiRtuptuO%08ot%025800251300100258258002513sp
derusaemerasretemarapllA ≤ .detonesiwrehtosselnuzHM056
.tniop
gnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauq
ehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttader
usaeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerast
uptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
853P022AG www.icst.com/products/hiperclocks.html REV. A FEBRUARY 23, 2005
5
Integrated
Circuit
Systems, Inc.
ICS853P022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
PARAMETER MEASUREMENT INFORMATION
OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
PROPAGATION DELAY
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME
SCOPE
Qx
nQx
LVPECL
2V
-1.8V to -1.0V
t
sk(pp)
t
sk(o)
nQx
Qx
nQy
Qy
PART 1
PART 2
nQx
Qx
nQy
Qy
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SWING
tp
LH
Q0, Q1
nQ0, nQ1
D0, D1
V
EE
V
CC
853P022AG www.icst.com/products/hiperclocks.html REV. A FEBRUARY 23, 2005
6
Integrated
Circuit
Systems, Inc.
ICS853P022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
3.3V LVPECL TRANSLATOR
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 1A and 1B
show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
FIGURE 1B. LVPECL OUTPUT TERMINATIONFIGURE 1A. LVPECL OUTPUT TERMINATION
V
CC
- 2V
50Ω 50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT
FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω 125Ω
84Ω 84Ω
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
APPLICATION INFORMATION
P1-P3P4-P6P7-P9P10-P11

ICS853P022AMLFT

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IC TRNSLTR UNIDIRECTIONAL 8SOIC
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