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LTC3828EUH#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
LTC3828
16
3828fc
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔI
L
decreases with higher
inductance or frequency and increases with higher V
IN
:
ΔI
fL
V
V
V
L OUT
OUT
IN
=
⎛
⎝
⎜
⎞
⎠
⎟
1
1
()( )
–
Accepting larger values of ΔI
L
allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔI
L
= 0.3(I
MAX
). The maximum
ΔI
L
occurs at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by R
SENSE
. Lower
inductor values (higher ΔI
L
) will cause this to occur at
lower load currents, which can cause a dip in effi ciency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Selection
Usually, high inductance is preferred for small current
ripple and low core loss. Unfortunately, increased induc-
tance requires more turns of wire or small air gap of the
inductor, resulting in high copper loss or low saturation
current. Once the value of L is known, the actual inductor
must be selected. There are two popular types of core
material of commercial available inductors.
Ferrite core inductors usually have very low core loss and
are preferred at high switching frequencies, so design
goals can concentrate on copper loss and preventing
saturation. However, ferrite core saturates “hard”, which
means that inductance collapses abruptly when the peak
design current is exceeded. This results in an abrupt in-
crease in inductor ripple current and consequent output
voltage ripple. One advantage of the LTC3828 is its current
mode control that detects and limits cycle-by-cycle peak
inductor current. Therefore, accurate and fast protection
is achieved if the inductor is saturated in steady state or
during transient mode.
Powder iron inductors usually saturate “soft”, which
means the inductance drops in a linear fashion when the
current increases. However, the core loss of the powder
iron inductor is usually higher than the ferrite inductor. So
design with high switching frequency should pay attention
to the inductor core loss too.
Inductor manufacturers usually provide inductance, DCR,
(peak) saturation current and (DC) heating current ratings
in the inductor data sheet. A good supply design should
not exceed the saturation and heating current rating of
the inductor.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for each
controller in the LTC3828: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV
CC
voltage.
This voltage is typically 5V during start-up. Consequently,
logic-level threshold MOSFETs must be used in most ap-
plications. The only exception is if low input voltage is ex-
pected (V
IN
< 5V); then, sub-logic level threshold MOSFETs
(V
GS(TH)
< 3V) should be used. Pay close attention to the
BV
DSS
specifi cation for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance, R
DS(ON)
, Miller capacitance, C
MILLER
, input
voltage and maximum output current. Miller capacitance,
C
MILLER
, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C
MILLER
is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
fl at divided by the specifi ed change in V
DS
. This result is
then multiplied by the ratio of the application applied V
DS
to the Gate charge curve specifi ed V
DS
. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main SwitchDuty Cycle
V
V
OUT
IN
=
APPLICATIONS INFORMATION
LTC3828
17
3828fc
Synchronous Switch Duty Cycle
VV
V
IN OUT
IN
=
–
The MOSFET power dissipations at maximum output
current are given by:
P
V
V
IR
V
I
RC
VVV
f
MAIN
OUT
IN
MAX DS ON
IN
MAX
DR MILLER
INTVCC THMIN THMIN
=
()
+
()
+
()
⎛
⎝
⎜
⎞
⎠
⎟
()( )
+
⎡
⎣
⎢
⎤
⎦
⎥
()
2
2
1
2
11
δ
()
•
–
P
VV
V
IR
SYNC
IN OUT
IN
MAX DS ON
=
()
+
()
–
()
2
1 δ
where δ is the temperature dependency of R
DS(ON)
and
R
DR
(approximately 2) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V
THMIN
is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I
2
R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V
IN
< 12V
the high current effi ciency generally improves with larger
MOSFETs, while for V
IN
≥ 12V the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
MILLER
actually provides higher effi ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead-
time and requiring a reverse recovery period that could
cost effi ciency at high V
IN
. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
C
IN
and C
OUT
Selection
The selection of C
IN
is simplifi ed by the multiphase ar-
chitecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst-case RMS current occurs
when only one controller is operating. The controller with
the highest (V
OUT
)(I
OUT
) product needs to be used in the
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease the
input RMS ripple current from this maximum value (see
Figure 3). The out-of-phase technique typically reduces
the input capacitor’s RMS ripple current by a factor of
30% to 70% when compared to a single phase power
supply solution.
The type of input capacitor, value and ESR rating have
effi ciency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
suffi cient to store adequate charge to keep high peak
battery currents down. 20µF to 40µF is usually suffi cient
for a 25W output supply operating at 260kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery effi ciency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used
as input capacitors, but each has drawbacks: ceramic
voltage coeffi cients are very high and may have audible
piezoelectric effects; tantalums need to be surge rated;
OS-CONs suffer from higher inductance, larger case size
and limited surface-mount applicability; electrolytics’
higher ESR and dryout possibility require several to be
used. Multiphase systems allow the lowest amount of
capacitance overall. As little as one 22µF or two to three
10µF ceramic capacitors are an ideal choice in a 20W to
35W power supply due to their extremely low ESR. Even
though the capacitance at 20V is substantially below their
rating at zero bias, very low ESR loss makes ceramics
APPLICATIONS INFORMATION
LTC3828
18
3828fc
an ideal candidate for highest effi ciency battery operated
systems. Also consider parallel ceramic and high quality
electrolytic capacitors as an effective means of achieving
ESR and bulk capacitance goals.
In continuous mode, the source current of the top N-chan-
nel MOSFET is a square wave of duty cycle V
OUT
/V
IN
. To
prevent large voltage transients, a low ESR input capaci-
tor sized for the maximum RMS current of one channel
must be used. The maximum RMS capacitor current is
given by:
C quiredI I
VVV
V
IN RMS MAX
OUT IN OUT
IN
Re
/
≈
−
()
[]
12
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even signifi cant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled
to meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
The benefi t of the LTC3828 multiphase clocking can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the interleaving of
current pulses through the input capacitor’s ESR. This is
why the input capacitor’s requirement calculated above for
the worst-case controller is adequate for the dual controller
design. Remember that input protection fuse resistance,
battery resistance and PC board trace resistance losses are
also reduced due to the reduced peak currents in a multi-
phase system. The overall benefi t of a multiphase design
will only be fully realized when the source impedance of
the power supply/battery is included in the effi ciency test-
ing. The drains of the two top MOSFETS should be placed
within 1cm of each other and share a common C
IN
(s).
Separating the drains and C
IN
may produce undesirable
voltage and current resonances at V
IN
.
The selection of C
OUT
is driven by the required output
voltage ripple and load transient response. Both the ca-
pacitor effective series resistance (ESR) and capacitance
determine the output ripple:
ΔV I ESR
fC
OUT L
OUT
≈Δ +
⎛
⎝
⎜
⎞
⎠
⎟
•
1
8
where f = operating frequency, C
OUT
= output capacitance
and ΔI
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔI
L
increases
with input voltage.
Usually, ceramic capacitors are used to minimize the output
voltage ripple because of their ultralow ESR. Currently,
multilayer ceramic capacitors have capacitor values up to
hundreds of µF. However, the capacitance of the ceramic
capacitors usually decreases with increased DC bias volt-
age and ambient temperature. In general, X5R or X7R type
capacitors are recommended for high performance solu-
tions. The OPTI-LOOP current mode control of LTC3828
provides stable, high performance transient response
even with all ceramic output capacitors. Manufactures
such as TDK, Taiyo Yuden, Murata and AVX provide high
performance ceramic capacitors.
When high capacitance is needed, especially for load
transient requirement, low ESR polymerized electrolytic
capacitors such as Sanyo POSCAP or Panasonic SP capaci-
tor can be used in parallel with ceramic capacitors. Other
high performance electolytic capacitor manufacturers
include AVX, KEMET and NEC. With LTC3828, a com-
bination of ceramic and low ESR electrolytic capacitors
can provide a low ripple, fast transient, high density and
cost-effective solution. Consult manufacturers for specifi c
recommendations.
INTV
CC
Regulator
An internal P-channel low dropout regulator produces 5V
at the INTV
CC
pin from the V
IN
supply pin. INTV
CC
powers
the drivers and internal circuitry within the IC. The INTV
CC
pin regulator can supply a peak current of 50mA and must
be bypassed to ground with a minimum of 4.7µF tantalum,
10µF special polymer, or low ESR type electrolytic capaci-
tor. A 1µF ceramic capacitor placed directly adjacent to the
INTV
CC
and PGND IC pins is highly recommended. Good
APPLICATIONS INFORMATION
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LTC3828EUH#PBF

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Buy LTC3828EUH#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual, 2-Phase Controller, w/ Tracking PLL
Lifecycle:
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