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NLV74HC14ADTR2G

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 14
1 Publication Order Number:
MC74HC14A/D
MC74HC14A
Hex Schmitt-Trigger
Inverter
High−Performance Silicon−Gate CMOS
The MC74HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
The HC14A is useful to “square up” slow input rise and fall times.
Due to hysteresis voltage of the Schmitt trigger, the HC14A finds
applications in noisy environments.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 60 FETs or 15 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
Y1A1
A2
A3
A4
A5
A6
Y2
Y3
Y4
Y5
Y6
1
3
5
9
11
13
2
4
6
8
10
12
Y = A
Pin 14 = V
CC
Pin 7 = GND
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
TSSOP−14
DT SUFFIX
CASE 948G
SOIC−14 NB
D SUFFIX
CASE 751A
HC14AG
AWLYWW
1
14
HC
14A
ALYWG
G
1
14
(Note: Microdot may be in either location)
TSSOP−14
SOIC−14 NB
PIN ASSIGNMENT
1314 12 11 10 9 8
21 34567
V
CC
A6 Y6 A5 Y5 A4 Y4
A1 Y1 A2 Y2 A3 Y3 GND
14−Lead (Top View)
L
H
FUNCTION TABLE
Inputs Outputs
A
H
L
Y
MC74HC14A
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature Range –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature Range, All Package Types –55 +125
_C
t
r
, t
f
Input Rise/Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
No Limit*
No Limit*
No Limit*
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*When V
in
= 50% V
CC
, I
CC
> 1mA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
circuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC14A
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3
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
V
Guaranteed Limit
Symbol Parameter Condition −55 to 25°C ≤85°C ≤125°C Unit
V
T+
max Maximum Positive−Going Input
Threshold Voltage
(Figure 3)
V
out
= 0.1V
|I
out
| ≤ 20mA
2.0
3.0
4.5
6.0
1.50
2.15
3.15
4.20
1.50
2.15
3.15
4.20
1.50
2.15
3.15
4.20
V
V
T+
min Minimum Positive−Going Input
Threshold Voltage
(Figure 3)
V
out
= 0.1V
|I
out
| ≤ 20mA
2.0
3.0
4.5
6.0
1.0
1.5
2.3
3.0
0.95
1.45
2.25
2.95
0.95
1.45
2.25
2.95
V
V
T−
max Maximum Negative−Going Input
Threshold Voltage
(Figure 3)
V
out
= V
CC
− 0.1V
|I
out
| ≤ 20mA
2.0
3.0
4.5
6.0
0.9
1.4
2.0
2.6
0.95
1.45
2.05
2.65
0.95
1.45
2.05
2.65
V
V
T−
min Minimum Negative−Going Input
Threshold Voltage
(Figure 3)
V
out
= V
CC
− 0.1V
|I
out
| ≤ 20mA
2.0
3.0
4.5
6.0
0.3
0.5
0.9
1.2
0.3
0.5
0.9
1.2
0.3
0.5
0.9
1.2
V
V
H
max
(Note 1)
Maximum Hysteresis Voltage
(Figure 3)
V
out
= 0.1V or V
CC
− 0.1V
|I
out
| ≤ 20mA
2.0
3.0
4.5
6.0
1.20
1.65
2.25
3.00
1.20
1.65
2.25
3.00
1.20
1.65
2.25
3.00
V
V
H
min
(Note 1)
Minimum Hysteresis Voltage
(Figure 3)
V
out
= 0.1V or V
CC
− 0.1V
|I
out
| ≤ 20mA
2.0
3.0
4.5
6.0
0.20
0.25
0.40
0.50
0.20
0.25
0.40
0.50
0.20
0.25
0.40
0.50
V
V
OH
Minimum High−Level Output
Voltage
V
in
≤ V
T−
min
|I
out
| ≤ 20mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
≤ V
T−
min |I
out
| ≤ 2.4mA
|I
out
| ≤ 4.0mA
|I
out
| ≤ 5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low−Level Output
Voltage
V
in
≥ V
T+
max
|I
out
| ≤ 20mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
≥ V
T+
max |I
out
| ≤ 2.4mA
|I
out
| ≤ 4.0mA
|I
out
| ≤ 5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0mA
6.0 1.0 10 40
mA
1. V
H
min > (V
T+
min) − (V
T−
max); V
H
max = (V
T+
max) − (V
T−
min).
AC CHARACTERISTICS (C
L
= 50pF, Input t
r
= t
f
= 6ns)
V
CC
V
Guaranteed Limit
Symbol Parameter −55 to 25°C ≤85°C ≤125°C Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Inverter)*
Typical @ 25°C, V
CC
= 5.0 V
pF
22
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
P1-P3P4-P6P7-P7

NLV74HC14ADTR2G

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Manufacturer:
ON Semiconductor
Description:
Logic Gates HEX SCHMITT-TRIGGER
Lifecycle:
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