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AD9572ACPZLVD-R7
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
AD9572
Rev. B | Page 12 of
20
50
Ω
50
Ω
50
Ω
50
Ω
50
Ω
50
Ω
50
Ω
50
Ω
50
Ω
07498-025
C
D
V
S
C
D
V
S
0.22µ
F
V
S
V
S
V
S
C
D
50
Ω
50
Ω
C
D
V
S
C
D
V
S
25MHz
C
X
= 22pF
C
X
= 22pF
50
Ω
T
O CMOS
INPU
T
C
D
= 100n
F|
|10n
F
C
D
C
D
V
S
V
S
C
D
V
S
C
D
V
S
C
D
0.22µ
F
V
S
C
D
V
S
C
D
V
S
C
D
V
S
TO CM
OS
IN
PUT
AD9572
106M
100M/
125M
VS
VS
VS
VS
33M
FREQSEL
106M
106M
VS
VS
VS
VS
GN
D
GN
D
NC
VS
25M
VS
XO
XO
REFCL
K
REFSEL
GN
D
BYP
ASS1
TES
T
FO
RCE_LO
W
VS
TEST
TEST
VS
VS
156M
100M/1
25M
BYPASS2
106M
100M/
125M
100M/
125M
156M
VS
VS
127
Ω
127
Ω
83
Ω
83
Ω
V
S
V
S
127
Ω
127
Ω
83
Ω
83
Ω
VS
V
S
127
Ω
127
Ω
127
Ω
127
Ω
83
Ω
83
Ω
83
Ω
83
Ω
VS
VS
127
Ω
127
Ω
83
Ω
83
Ω
Figure 8. Typic
al Applicati
on Schematic, L
PECL Format Out
puts, 1 × 25 MH
z, 1 × 156.25
MHz, 2 × 125 M
Hz, and 2 × 10
6.25 MHz
AD9572
Rev. B | Page 13 of
20
TYPICAL PERFORMANCE CHARACTE
RISTICS
Phase noise plots tak
en
with 100 MHz and 125 MHz o
utputs ena
bled; 33.3 MHz outp
ut disabled.
07498-0
08
–
100
–160
–150
–140
–130
–120
–110
1k
10k
100
k
1M
100M
10M
PHASE NO
ISE
(dBc/
Hz)
FREQ
UENCY (Hz
)
07498-0
11
–
100
–160
–150
–140
–130
–120
–110
1k
10k
100k
1M
100M
10M
PHASE NO
ISE
(dBc/
Hz)
FREQ
UENCY (Hz
)
Figure 9. 1
06.25 MHz Ph
ase Noise
Figure 12. 156.25
MHz Phase Noise
07498-0
09
–
100
–160
–150
–140
–130
–120
–110
1k
10k
100
k
1M
100M
10M
PHASE NO
ISE
(dBc/
Hz)
FREQ
UENCY (Hz
)
07498-0
12
–
100
–160
–150
–140
–130
–120
–110
1k
10k
100k
1M
100M
10M
PHASE NO
ISE
(dBc/
Hz)
FREQ
UENCY (Hz
)
Figure 10. 12
5 MHz Phas
e Noise
Figure 13. 10
0 MHz Phas
e Noise
07498-0
10
–
100
–160
–150
–140
–130
–120
–110
1k
10k
100k
1M
100M
10M
PHASE NO
ISE
(dBc/
Hz)
FREQ
UENCY (
Hz)
10ns/
DIV
500mV/
DI
V
07498-026
Figure 14. 25 MHz
CMOS Output, 3.9 pF Load Capac
itance on Evaluation
Board, Active-Probe
Measurement, R
probe
=20 kΩ, C
probe
=1 pF
Figure 11. 25 MHz
Phase Noise
AD9572
Rev. B | Page 14 of
20
2ns/
DI
V
200mV/
DI
V
07498-027
Figure 15. 156.
25 MHz LVPE
CL Output, Differenti
al Plot, 200 Ω
Terminatio
n
to GND on Evaluation Board, AC-C
oupled via 0.1 μF Capacit
ors to
Oscilloscope Set t
o 50 Ω Input
Termination
2ns/
DI
V
100mV/
DI
V
07498-028
Figure 16. 125 M
Hz LVDS Output, Diff
erential Plot, AC-C
oupled via 0.
1 μF
Capacitors to Oscilloscope Set to 50 Ω Input Termination
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
AD9572ACPZLVD-R7
Mfr. #:
Buy AD9572ACPZLVD-R7
Manufacturer:
Analog Devices Inc.
Description:
Clock Drivers & Distribution Fiber CH/ PLL Core 7 Clock Output
Lifecycle:
New from this manufacturer.
Delivery:
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