NCP5901MNTBG

© Semiconductor Components Industries, LLC, 2013
June, 2013 Rev. 2
1 Publication Order Number:
NCP5901/D
NCP5901
VR12 Compatible
Synchronous Buck MOSFET
Drivers
The NCP5901 is a high performance dual MOSFET gate driver
optimized to drive the gates of both highside and lowside power
MOSFETs in a synchronous buck converter. It can drive up to 3 nF
load with a 25 ns propagation delay and 20 ns transition time.
Adaptive anticrossconduction and power saving operation
circuit can provide a low switching loss and high efficiency solution
for notebook and desktop systems. Bidirectional EN pin can provide
a fault signal to controller when the gate driver fault detect under
OVP, UVLO occur. Also, an undervoltage lockout function
guarantees the outputs are low when supply voltage is low.
Features
Faster Rise and Fall Times
Adaptive AntiCrossConduction Circuit
Pre OV function
ZCD Detect
Floating Top Driver Accommodates Boost Voltages of up to 35 V
Output Disable Control Turns Off Both MOSFETs
Undervoltage Lockout
Power Saving Operation Under Light Load Conditions
Direct Interface to NCP6151 and Other Compatible PWM
Controllers
Thermally Enhanced Package
These are PbFree Devices
Typical Applications
Power Solutions for Desktop Systems
SOIC8 NB
D SUFFIX
CASE 751
Device Package Shipping
ORDERING INFORMATION
NCP5901MNTBG DFN8
(PbFree)
3000 / Tape & Reel
http://onsemi.com
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
8
DFN8
MN SUFFIX
CASE 506AA
NCP5901DR2G SOIC8
(PbFree)
2500 / Tape & Reel
N5901 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
MARKING DIAGRAMS
N5901
ALYW
G
1
8
AJ = Specific Device Code
M = Date Code
G = PbFree Device
AJMG
G
1
1
NCP5901
http://onsemi.com
2
Figure 1. Pin Diagram
DRVH
SW
GND
DRVL
BST
PWM
EN
VCC
1
FLAG
(Top View)
9
BST
PWM
Logic
DRVH
SW
AntiCross
Conduction
VCC
DRVL
VCC
EN
Fault
UVLO
PreOV
ZCD
Detection
Figure 2. Block Diagram
Table 1. Pin Descriptions
Pin No. Symbol Description
1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin
and the SW pin.
2 PWM Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode
Emulation Enabled, High = High Side FET Enabled.
3 EN Logic input. A logic high to enable the part and a logic low to disable the part.
4 VCC Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground.
5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET.
6 GND Bias and reference ground. All signals are referenced to this node (QFN Flag).
7 SW Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET.
8 DRVH High side gate drive output. Connect to the gate of high side MOSFET.
9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane.
NCP5901
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3
Figure 3. Application Circuit
VREG_SW1_HG
VCCP
TP3
VREG_SW1_OUT
VREG_SW1_LG
TP6
TP7
TP8
TP4
TP1
TP2
TP5
NTMFS4851N NTMFS4851N
Q9 Q10
NTMFS4821N
Q1
MMSD4148
CR1
NCP5901
BST
PWM
EN
VCC
HG
SW
GND
LG
PAD
DRON
PWM
CSN11
CSP11
C1 C2 C3 CE9
L
R3
C6
R164
12V_POWER
R1
R143
C4
0.027uF
0.0
1.02
C5
1uF
R142
0.0
0.0
2.2
2700pF
235nH
4.7uF 4.7uF 4.7uF 390uF
+
JP13_ETCH
JP14_ETCH
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol Pin Name V
MAX
V
MIN
VCC Main Supply Voltage Input 15 V 0.3 V
BST Bootstrap Supply Voltage 35 V wrt/ GND
40 V 50 ns wrt/ GND
15 V wrt/ SW
0.3 V wrt/SW
SW Switching Node
(Bootstrap Supply Return)
35 V
40 V 50 ns
5 V
10 V (200 ns)
DRVH High Side Driver Output BST+0.3 V 0.3 V wrt/SW
2 V (<200 ns) wrt/SW
DRVL Low Side Driver Output VCC+0.3 V 0.3 V DC
5 V (<200 ns)
PWM DRVH and DRVL Control Input 6.5 V 0.3 V
EN Enable Pin 6.5 V 0.3 V
GND Ground 0 V 0 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. THERMAL INFORMATION (All signals referenced to AGND unless noted otherwise)
Symbol Parameter Value Unit
R
q
JA
Thermal Characteristic SOIC Package (Note 1)
DFN Package (Note 1)
123
74
°C/W
T
J
Operating Junction Temperature Range (Note 2) 0 to 150 °C
T
A
Operating Ambient Temperature Range 10 to +125 °C
T
STG
Maximum Storage Temperature Range 55 to +150 °C
MSL Moisture Sensitivity Level SOIC Package
DFN Package
1
1
* The maximum package power dissipation must be observed.
1. I in
2
Cu, 1 oz thickness.
2. Operation at 40°C to 10°C guaranteed by design, not production tested.

NCP5901MNTBG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers VR12 MOSFET DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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