© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 11
1 Publication Order Number:
MC10EP31/D
MC10EP31, MC100EP31
3.3V / 5V ECL D Flip‐Flop
with Set and Reset
Description
The MC10/100EP31 is a D flip-flop with set and reset. The device is
pin and functionally equivalent to the EL31 and LVEL31 devices.
With AC performance much faster than the EL31 and LVEL31
devices, the EP31 is ideal for applications requiring the fastest AC
performance available. Both set and reset inputs are asynchronous,
level triggered signals. Data enters the master portion of the flip-flop
when CLK is low and is transferred to the slave, and thus the outputs,
upon a positive transition of the CLK.
The 100 Series contains temperature compensation.
Features
• 340 ps Typical Propagation Delay
• Maximum Frequency = > 3 GHz Typical
• PECL Mode Operating Range:
V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
• NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V
EE
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
SOIC−8 NB
D SUFFIX
CASE 751−07
MARKING DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R−02
ALYWG
G
HP31
ALYWG
G
KP31
1
8
1
8
1
8
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D
.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
8
HEP31
ALYW
G
1
8
KEP31
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
(Note: Microdot may be in either location)
SOIC−8 NB TSSOP−8 DFN8
5O MG
G
14
3J MG
G
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb-Free Package
H = MC10
K = MC100
5O = MC10
3J = MC100
M
= Date Code
