LTC4416IMS-1#PBF

LTC4416/LTC4416-1
4
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TYPICAL PERFOR A CE CHARACTERISTICS
U W
V
RTO
vs Temperature and Supply
Voltage
SUPPLY VOLTAGE (V)
0
20
V
FR
(mV)
25
30
35
40
5 10 15 20
4416 G01
25
27°C
30 35 40
–40°C
125°C
SUPPLY VOLTAGE (V)
0
V
RTO
(mV)
–22
–21
–20
15 25 40
4416 G02
–23
–24
–25
5 10
20
30 35
–40°C
125°C
27°C
TEMPERATURE (°C)
–50
0.80
CURRENT (A)
0.90
1.00
1.10
1.20
–25 0 25 50
4416 G03
75 100 125 150
NORMALIZED AT
V
IN
= 3.6V
V
IN
= 20V
V
IN
= 36V
V
V1
= V
V2
= V
VS
= V
VIN
3.6V V
VIN
36V
Normalized Quiescent Supply
Current vs Temperature
V
FR
vs Temperature and Supply
Voltage
V
Gn(ON)
vs Temperature and V
IN
V1, V2 and V
S
Pin Leakage vs
Temperature
TEMPERATURE (°C)
–50
CURRENT (µA)
–1.00
–0.75
150
4416 G04
–1.25
–1.50
0
50
100
–0.25
–0.50
I
V1
: V
V2
, V
VS
– V
V1
= 28V
I
V2
: V
V1
, V
VS
– V
V2
= 28V
I
VS
: V
V1
, V
V2
– V
VS
= 28V
TEMPERATURE (°C)
–50
8.65
8.75
8.95
100
4416 G05
8.55
8.45
0 50 150
8.35
8.25
8.85
V
Gn(ON)
(V)
V
IN
= 10V
I
Gn
= 2µA
V
V1
= V
V2
= V
VIN
V
VS
= V
VIN
– 200mV
V
IN
= 36V
TEMPERATURE (°C)
–50
V
Gn(OFF)
(V)
0.20
0.30
150
4416 G06
0.10
0
0
50
100
0.50
0.40
I
Gn
= 0µA
I
Gn
= –10µA
I
Gn
= –20µA
3.6V V
V1
V
V2
36V
V
VS
= V
VIN
+ 200mV
V
Gn(OFF)
vs Temperature and I
Gn
t
G(ON)
vs Temperature t
G(OFF)
vs Temperature
TEMPERATURE (°C)
–50
t
G(ON)
(µs)
50
75
150
4416 G07
25
0
0
50
100
100
t
G(ON)
(µs) AT 10V
t
G(ON)
(µs) AT 36V
C
Gn
= 15nF
V
VS
= V
VIN
– 200mV
10V V
V1
V
V2
36V
TEMPERATURE (°C)
50
t
G(OFF)
(µs)
35
40
45
150
4416 G08
30
25
15
0
50
100
20
55
50
t
G(OFF)
(µs) AT 10V
t
G(OFF)
(µs) AT 36V
C
Gn
= 15nF
V
VS
= V
VIN
+ 200mV
10V V
V1
V
V2
36V
LTC4416/LTC4416-1
5
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PI FU CTIO S
U U U
H1 (Pin 1): Open-Drain Comparator Output of the E1 Pin.
If E1 > V
REF
, the H1 pin will go high impedance, otherwise
the pin will be grounded. The maximum voltage permitted
on this pin is 7V. This pin provides support for setting up
hysterisis to an external resistor network.
E1 (Pin 2): LTC4416 Comparator Enable Input. A high
signal greater than V
REF
will enable the V1 path. The ideal
diode action will then determine if the V1 path should turn
on by controlling any PFET(s) connected to the G1 pin.
If the E1 signal is driven low, the V1 path will perform a
“soft-off” provided the PFET(s) are properly configured
for blocking DC current. An internal current sink will pull
the E1 pin down when the E1 input exceeds 1.5V.
E1 (Pin 2): LTC4416-1 Comparator Enable Input. A high
signal greater than V
REF
will enable the V1 path. The ideal
diode action will then determine if the V1 path should turn
on by controlling any PFET(s) connected to the G1 pin.
If the E1 signal is driven low, the V1 path will be quickly
disabled by enabling the “fast-off” feature, pulling the G1
gate high. An internal current sink will pull the E1 pin down
when the E1 input exceeds 1.5V.
GND (Pin 3): Ground. This pin provides a power return
path for all the internal circuits.
E2 (Pin 4): LTC4416 Comparator Enable Input. A low
signal less than V
REF
will enable the V2 path. The ideal
diode action will then determine if the V2 path should turn
on by controlling any PFET(s) connected to the G2 pin.
If the E2 signal is driven high, the V2 path will perform a
“soft-off” provided the PFET(s) are properly configured
for blocking DC current. An internal current sink will pull
the E2 pin down when the E2 input exceeds 1.5V.
E2 (Pin 4): LTC4416-1 Comparator Enable Input. A low
signal less than V
REF
will enable the V2 path. The ideal
diode action will then determine if the V2 path should turn
on by controlling any PFET(s) connected to the G2 pin.
If the E2 signal is driven high, the V2 path will be quickly
disabled by enabling the “fast-off” feature, pulling the G2
gate high. An internal current sink will pull the E2 pin down
when the E2 input exceeds 1.5V.
H2 (Pin 5): Open-Drain Comparator Output of the E2 Pin.
If E2 > V
REF
, the H2 pin will go high impedance, otherwise
the pin will be grounded. The maximum voltage permitted
on this pin is 7V. This pin provides support for setting up
hysterisis to an external resistor network.
G2 (Pin 6): Second P-Channel MOSFET Power Switch
Gate Drive Pin. This pin is directed by the second power
controller to maintain a forward regulation voltage (V
FR
)
of 25mV between the V2 and V
S
pins when V2 is greater
than V
S
. When V2 is less than V
S
, the G2 pin will pull up
to the V
S
pin voltage, turning off the second P-channel
power switch.
V2 (Pin 7): Second Input Supply Voltage. Supplies power
to the second power controller and the band-gap refer-
ence. V2 is one of the two voltage sense inputs to the
second internal power controller (the other input to the
second internal power controller is the V
S
pin). This input
is usually supplied power from the second, or backup,
power source. This pin can be bypassed to ground with
a capacitor in the range of 0.1µF to 10µF if needed to
suppress load transients.
V
S
(Pin 8): Power Sense Input Pin. Supplies power to
the internal circuitry of both the first and second power
controller and the band-gap reference. This pin is also a
voltage sense input to both internal analog controllers
(the other input to the first controller is the V1 pin and
the other input to the second controller is the V2 pin.)
This input may also be supplied power from an auxiliary
source which also supplies current to the load.
V1 (Pin 9): First Input Supply Voltage. Supplies power to
the first power controller and the band-gap reference. V1
is one of the two voltage sense inputs to the first internal
power controller (the other input to the first internal power
controller is the V
S
pin). This input is usually supplied
power from the first, or primary, power source. This pin
can be bypassed to ground with a capacitor in the range
of 0.1µF to 10µF if needed to suppress load transients.
G1 (Pin 10): First P-Channel MOSFET Power Switch Gate
Drive Pin. This pin is directed by the first power controller
to maintain a forward regulation voltage (V
FR
) of 25mV
between the V1 and V
S
pins when V1 is greater than V
S
.
When V1 is less than V
S
, the G1 pin will pull up to the V
S
pin
voltage, turning off the first P-channel power switch.
LTC4416/LTC4416-1
6
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BLOCK DIAGRA
W
V
REF
E2
4
V2
7
+
V
REF
E1
2
GND
3
V
S
8
V1
9
+
A2
C2
RAIL2
RAIL1
SECOND
ANALOG
CONTROLLER
BAND-GAP
REFERENCE
I
G(SRC)
I
G(OFF)
I
G2
8.5V
G2
H2
I
G(SNK)
I
GFON(SNK)
6
A1
FIRST
ANALOG
CONTROLLER
I
G(SRC)
I
G(OFF)
8.5V
G1
I
G(SNK)
V
REF
RAILBG
I
GFON(SNK)
10
4416 BD
5
H1
1
EN2
EN2
EN1
EN1
EN2
EN1
C1
I
G1
Operation can best be understood by referring to the
Block Diagram which illustrates the internal circuit blocks.
The LTC4416/LTC4416-1 are divided into three sections,
namely:
1. The channel 1 controller consisting of A1, C1, the “first
analog contoller,” the G1 drivers and the H1 output
driver.
2. The band-gap reference
3. The channel 2 controller consisting of A2, C2, the
“second analog controller,” the G2 drivers and the H2
output driver.
Each of the three sections has its own derived internal
power supply referred to as a rail. RAIL1 provides power
to the channel 1 controller. RAIL2 provides power to the
channel 2 controller. The internal RAILBG provides power
to the band-gap reference. The internal rail1 derives its
power from the higher voltage of V1 and V
S
. The internal
rail2 derives its power from the higher voltage of V2 and
V
S
. RAILBG derives its power from the highest voltage of
V1, V2, and V
S
. All three sections share a common ground
connected to the GND pin.
OPERATIO
U

LTC4416IMS-1#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC 36V, L Loss 2x PwrPath Cntrs for Lrg PFE
Lifecycle:
New from this manufacturer.
Delivery:
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