PRH601 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 10 March 2016
219233 7 of 15
NXP Semiconductors
PRH601
Multi-frequency integrated reader solution
9.2 Pin description
For a description of the detailed pin functionality refer to the relevant product data sheet.
VSS and GND refer to the same signal and need all be connected.
10. Functional description
The functionality of this device is defined by the functionality of the three chips CLRC663,
HTRC110 and LPC1227. No internal connection of the devices had been implemented
except for the GND signal. All external available GND signals need to be connected. A
design making use of this device shall consider a sufficient low thermal resistance
between package and environment. All pins are recommended to be connected to defined
signal levels. A PCB design using the PRH600 shall make use of state of the art design
practices to ensure a sufficient heat dissipation. For a detailed functionality refer to the
latest product specifications of the CLRC663, HTRC110 and LPC1227.
79 PIO0_19 LPC1227
80 PIO0_20 LPC1227
81 PIO0_21 LPC1227
82 PIO0_22 LPC1227
83 PIO0_23 LPC1227
84 PIO0_24 LPC1227
85 PIO0_25 LPC1227
86 PIO0_26 LPC1227
87 PIO0_27 LPC1227
88 GND all
89 PIO0_28 LPC1227
90 PIO0_29 LPC1227
91 PIO0_0 LPC1227
92 PIO0_1 LPC1227
93 PIO0_2 LPC1227
94 PIO0_3 LPC1227
95 PIO0_4 LPC1227
96 PIO0_5 LPC1227
97 PIO0_6 LPC1227
98 PIO0_7 LPC1227
99 PIO0_8 LPC1227
100 PIO0_9 LPC1227
Table 4. Pin allocation table
…continued
Pin Symbol Connection
