MAX1401
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
22 ______________________________________________________________________________________
Table 11. Channel ID Tag Codes
Switching Network
A switching network provides selection between three
fully differential input channels or five pseudo-differen-
tial channels, using AIN6 as a shared common. The
switching network provides two additional fully differen-
tial input channels intended for system calibration,
which may be used as extra fully differential signal
channels. Table 12 shows the channel configurations
available for both operating modes.
Scanning (SCAN Mode)
To sample and convert the available input channels
sequentially, set the SCAN control bit in the global
setup register. The sequence is determined by DIFF
(fully differential or pseudo-differential) and by the
mode control bits M1 and M0 (Tables 8, 9, and 10).
With SCAN set, the part automatically sequences
through each available channel, transmitting a single
conversion result before proceeding to the next chan-
nel. The MAX1401 automatically allows sufficient time
for each conversion to fully settle, to ensure optimum
resolution before asserting the data-ready signal and
moving to the next available channel. The scan rate,
therefore, depends on the clock bit (CLK), the filter
control bits (FS1, FS0), and the modulator frequency
selection bits (MF1, MF0).
Burn-Out Currents
The input circuitry also provides two “burn-out” cur-
rents. These small currents may be used to test the
integrity of the selected transducer. They can be selec-
tively enabled or disabled by the BOUT bit in the global
setup register.
CHANNELCID2
1
1
AIN1–AIN2
AIN5–AIN6
1 Calibration11
01
1 AIN3–AIN410
00
0
0
AIN1–AIN6
AIN3–AIN6
0 AIN4–AIN611
01
0 AIN2–AIN610
CID0
0
CID1
0
Table 12. Input Channel Configuration in Fully Differential and Pseudo-Differential
Mode (SCAN = 0)
X = Don’t care
* This combination is available only in pseudo-differential mode when using the internal scanning logic.
** These combinations are only available in the calibration modes.
0
M0
0
DIFF
0 0 AIN20
0 0
0 0 AIN40
AIN3
AIN1
0
0
0 1
0 1 AIN30
0 1
1 X CALOFF+**0
AIN5
AIN1
0
0
0 X
1 X CALOFF+**
M1
0
0 X
HIGH INPUT
CALGAIN+**
AIN5*
1
0
0 X CALGAIN+**1
0
A1
0
1
1
0
0
1
X
X
X
X
X
MODE
Pseudo-
Differential
Fully
Differential
0
A0
1
0
1
0
1
0
X
X
X
X
X
AIN6
AIN6
AIN6
AIN6
AIN4
CALOFF-**
AIN6
AIN2
CALOFF-**
LOW INPUT
CALGAIN-**
AIN6*
CALGAIN-**
MAX1401
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________ 23
External Access to Mux Outputs
The MAX1401 provides access to the switching-net-
work output and the modulator input with the MUXOUT
and ADCIN pins. This allows the user to share a single
high-performance amplifier for additional signal condi-
tioning of all input channels.
Dynamic Input Impedance at the
Channel Selection Network
When used in unbuffered mode (BUFF = 0), the analog
inputs present a dynamic load to the driving circuitry.
The size of the sampling capacitor and the input sam-
pling frequency (Figure 5) determine the dynamic load
seen by the driving circuitry. The MAX1401 samples at a
constant rate for all gain settings. This provides a maxi-
mum time for the input to settle at a given data rate. The
dynamic load presented by the inputs varies with the
gain setting. For gains of +2V/V, +4V/V, and +8V/V, the
input sampling capacitor increases with the chosen
gain. Gains of +16V/V, +32V/V, +64V/V, and +128V/V
present the same input load as the x8 gain setting.
When designing with the MAX1401, as with any other
switched-capacitor ADC input, consider the advan-
tages and disadvantages of series input resistance. A
series resistor reduces the transient-current impulse to
the external driving amplifier. This improves the amplifi-
er phase margin and reduces the possibility of ringing.
The resistor spreads the transient-load current from the
sampler over time due to the RC time constant of the
circuit. However, an improperly chosen series resis-
tance can hinder performance in fast 16-bit converters.
The settling time of the RC network can limit the speed
at which the converter can operate properly, or reduce
the settling accuracy of the sampler. In practice, this
means ensuring that the RC time constant—resulting
from the product of the driving source impedance and
the capacitance presented by both the MAX1401’s
input and any external capacitances—is sufficiently
small to allow settling to the desired accuracy. Tables
13a–13d summarize the maximum allowable series
resistance vs. external capacitance for each MAX1401
gain setting in order to ensure 16-bit performance in
unbuffered mode.
R
EXT
C
EXT
R
MUX
C
PIN
MUXOUT ADCIN
R
SW
C
ST
C
PIN
C
SAMPLE
C
C
Figure 5. Analog Input, Unbuffered Mode (BUFF = 0)
Table 13a. R
EXT
, C
EXT
Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode; 1x Modulator Sampling Frequency (MF1, MF0 = 00); X2CLK = 0; f
CLKIN
= 2.4576MHz
Table 13b. R
EXT
, C
EXT
Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode; 2x Modulator Sampling Frequency (MF1, MF0 = 00); X2CLK = 0; f
CLKIN
= 2.4576MHz
29 14
29 14 9.42
22 12
15 9.6 7.0
8, 16, 32,
64, 128
8.4
9.4
4
1
C
EXT
= 0pF C
EXT
= 50pF C
EXT
= 100pF
2.9 1.6
2.9 1.6 0.43
2.7 1.5
2.4 1.4 0.37
0.40
PGA GAIN
0.43
C
EXT
= 500pF C
EXT
= 1000pF C
EXT
= 5000pF
EXTERNAL RESISTANCE, R
EXT
(k)
14 6.9
14 6.9 4.72
11 6.0
7.7 4.8 3.5
8, 16, 32,
64, 128
4.2
4.7
4
1
C
EXT
= 0pF C
EXT
= 50pF C
EXT
= 100pF
1.4 0.81
1.4 0.81 0.22
1.3 0.76
1.2 0.70 0.18
0.20
PGA GAIN
0.22
C
EXT
= 500pF C
EXT
= 1000pF C
EXT
= 5000pF
EXTERNAL RESISTANCE, R
EXT
(k)
MAX1401
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
24 ______________________________________________________________________________________
Input Buffers
The MAX1401 provides a pair of input buffers to isolate
the inputs from the capacitive load presented by the
PGA/modulator (Figure 6). The buffers are chopper sta-
bilized to reduce the effect of their DC offsets and low-
frequency noise. Since the buffers can represent more
than 50% of the total analog power dissipation, they
may be shut down in applications where minimum
power dissipation is required and the capacitive input
load is not a concern. Disable the buffers in applications
where the inputs must operate close to AGND or V+.
When used in buffered mode, the buffers isolate the
inputs from the sampling capacitors. The sampling-
related gain error is dramatically reduced in this mode.
A small dynamic load remains from the chopper stabi-
lization. The multiplexer exhibits a small input leakage
current of up to 10nA. With high source resistances,
this leakage current may result in a DC offset.
Table 13c. R
EXT
, C
EXT
Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode; 4x Modulator Sampling Frequency (MF1, MF0 = 10 ); X2CLK = 0; f
CLKIN
=
2.4576MHz
Table 13d. R
EXT
, C
EXT
Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode; 8x Modulator Sampling Frequency (MF1, MF0 = 11); X2CLK = 0; f
CLKIN
=
2.4576MHz
R
EXT
C
EXT
R
MUX
C
PIN
MUXOUT
ADCIN
R
IN
C
ST
C
PIN
C
AMP
C
SAMPLE
C
C
Figure 6. Analog Input, Buffered Mode (BUFF = 1)
7.0 3.4
7.0 3.4 2.32
5.5 3.0
3.8 2.4 1.7
8, 16, 32,
64, 128
2.1
2.3
4
1
C
EXT
= 0pF C
EXT
= 50pF C
EXT
= 100pF
0.71 0.40
0.71 0.40 0.11
0.66 0.38
0.60 0.34 0.09
0.10
PGA GAIN
0.11
C
EXT
= 500pF C
EXT
= 1000pF C
EXT
= 5000pF
EXTERNAL RESISTANCE, R
EXT
(k)
3.4 1.7
3.4 1.7 1.12
2.7 1.4
1.8 1.2 0.85
8, 16, 32,
64, 128
1.0
1.1
4
1
C
EXT
= 0pF C
EXT
= 50pF C
EXT
= 100pF
0.35 0.20
0.35 0.20 0.05
0.32 0.18
0.29 0.17 0.04
0.05
PGA GAIN
0.05
C
EXT
= 500pF C
EXT
= 1000pF C
EXT
= 5000pF
EXTERNAL RESISTANCE, R
EXT
(k)

MAX1401CAI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 18-Bit 5Ch 4.8ksps 1.25V Precision ADC
Lifecycle:
New from this manufacturer.
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