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NB7N017MMN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
NB7N017M
http://onsemi.com
13
Table 12. OPERATION TABLE
MR TCTC_INTCLK_INTCLKCESELPLbPbPLaPa
0 XXXXXXXX L XXXXXXXX L H H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L H H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X L H H X X
0 XXXXXXXX L XXXXXXXX L X L L H X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X L H H X X
0 XXXXXXXX L XXXXXXXX L X H L H X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X L L L X X
0 00000010 H XXXXXXXX L X H H H X X
0 XXXXXXXX L 00000001 H X H L L X X
0 XXXXXXXX L XXXXXXXX L H H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L L H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L L H L L X X
0 XXXXXXXX L XXXXXXXX L L H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
0 XXXXXXXX L XXXXXXXX L L H L L X X
0 XXXXXXXX L XXXXXXXX L L H H H X X
0 XXXXXXXX L XXXXXXXX L X H L L X X
0 XXXXXXXX L XXXXXXXX L X H H H X X
X − Don’t Care
H − HIGH
L − LOW
NB7N017M
http://onsemi.com
14
Figure 10. Device Timing Diagram for Table 12
Figure 11. Timing Diagram for CE Input
MR
Pa[7:0]
PLa
Pa_INT[7:0]
Pb[7:0]
PLb
Pb_INT[7:0]
SEL
CE
CLK
CLK_INT
TC_INT
TC
05 XX 02 XX
05 02
04 XX
01
XX
04 01
MR
CLK
CE
CLK_INT
NB7N017M
http://onsemi.com
15
Figure 12. Timing Diagram for PLa / PLb Inputs
(SEL is Low)
Figure 13. Timing Diagram for PLa / PLb Inputs
(Before Critical Rising Edge of CLK)
(SEL is Low)
MR
CLK
PLa
Pa[7:0]
TC[7:0]
0B
delay
d=12 d=12 d=12
MR
CLK
PLa
Pa[7:0]
TC[7:0]
0B
(hex)
d=12 d=12
Figure 14. Timing Diagram for PLa / PLb Inputs
(After Critical Rising Edge of CLK)
(SEL is Low)
MR
CLK
PLa
Pa[7:0]
TC[7:0]
0B
(hex)
d=256 d=12
d=256
delay
delay
d=256
d=256 d=256 d=256
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

NB7N017MMN

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Manufacturer:
ON Semiconductor
Description:
Prescaler BBG 8BT DL MOD
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