PESD5V0X1BQ_PESD5V0X1BT_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 30 October 2008 6 of 13
NXP Semiconductors
PESD5V0X1BQ; PESD5V0X1BT
Ultra low capacitance bidirectional ESD protection diodes
Fig 6. ESD clamping test setup and waveforms
006aab336
50
R
Z
C
Z
DUT
(DEVICE
UNDER
TEST)
GND
GND
450
RG 223/U
50 coax
ESD TESTER
IEC 61000-4-2 network
C
Z
= 150 pF; R
Z
= 330
4 GHz DIGITAL
OSCILLOSCOPE
10×
ATTENUATOR
GND
GND
unclamped +8 kV ESD pulse waveform
(IEC 61000-4-2 network)
clamped +8 kV ESD pulse waveform
(IEC 61000-4-2 network) pin 1 to 2
unclamped 8 kV ESD pulse waveform
(IEC 61000-4-2 network)
clamped 8 kV ESD pulse waveform
(IEC 61000-4-2 network) pin 1 to 2
vertical scale = 2 kV/div
horizontal scale = 15 ns/div
vertical scale = 20 V/div
horizontal scale = 100 ns/div
vertical scale = 20 V/div
horizontal scale = 100 ns/div
vertical scale = 2 kV/div
horizontal scale = 15 ns/div
PESD5V0X1BQ_PESD5V0X1BT_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 30 October 2008 7 of 13
NXP Semiconductors
PESD5V0X1BQ; PESD5V0X1BT
Ultra low capacitance bidirectional ESD protection diodes
7. Application information
PESD5V0X1BQ and PESD5V0X1BT are designed for the protection of one bidirectional
data or signal line from the damage caused by ESD. The devices may be used on lines
where the signal polarities are both, positive and negative with respect to ground.
PESD5V0X1BQ and PESD5V0X1BT may also be used for the protection of two
unidirectional data or signal lines, which have positive signal polarities with respect to
ground.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD and Electrical Fast
Transient (EFT). The following guidelines are recommended:
1. Place the device as close to the input terminal or connector as possible.
2. The path length between the device and the protected line should be minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
8. Test information
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard
Q101 - Stress test qualification for discrete semiconductors
, and is
suitable for use in automotive applications.
Fig 7. Application diagram
006aab252
bidirectional protection
of one line
DUT
line 1 to be protected
GND
DUT
line 1 to be protected
unidirectional protection
of two lines
line 2 to be protected
GND
PESD5V0X1BQ_PESD5V0X1BT_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 30 October 2008 8 of 13
NXP Semiconductors
PESD5V0X1BQ; PESD5V0X1BT
Ultra low capacitance bidirectional ESD protection diodes
9. Package outline
10. Packing information
[1] For further information and the availability of packing methods, see Section 14.
Fig 8. Package outline PESD5V0X1BQ (SOT663) Fig 9. Package outline
PESD5V0X1BT (SOT23/TO-236AB)
Dimensions in mm
02-05-21
1.7
1.5
1.7
1.5
1.3
1.1
1
0.18
0.08
0.33
0.23
0.5
12
3
0.6
0.5
0.3
0.1
04-11-04Dimensions in mm
0.45
0.15
1.9
1.1
0.9
3.0
2.8
2.5
2.1
1.4
1.2
0.48
0.38
0.15
0.09
12
3
Table 10. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.
[1]
Type number Package Description Packing quantity
3000 4000 8000 10000
PESD5V0X1BQ SOT663 2 mm pitch, 8 mm tape and reel - - -315 -
4 mm pitch, 8 mm tape and reel - -115 - -
PESD5V0X1BT SOT23 4 mm pitch, 8 mm tape and reel -215 - - -235

PESD5V0X1BT,215

Mfr. #:
Manufacturer:
Nexperia
Description:
TVS Diodes / ESD Suppressors DIODE ARRAY ESD 2L EXTREM LOW
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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