LT8612
16
8612f
For more information www.linear.com/LT8612
applicaTions inForMaTion
Output Power Good
When the LT8612’s output voltage is within the ±9%
window of the regulation point, which is a V
FB
voltage in
the range of 0.883V to 1.057V (typical), the output voltage
is considered good and the open-drain PG pin goes high
impedance and is typically pulled high with an external
resistor. Otherwise, the internal pull-down device will pull
the PG pin low. To prevent glitching both the upper and
lower thresholds include 1.3% of hysteresis.
The PG pin is also actively pulled low during several fault
conditions: EN/UV pin is below 1V, INTV
CC
has fallen too
low, V
IN
is too low, or thermal shutdown.
Synchronization
To select low ripple Burst Mode operation, tie the SYNC pin
below 0.4V (this can be ground or a logic low output). To
synchronize the LT8612 oscillator to an external frequency
connect a square wave (with 20% to 80% duty cycle) to
the SYNC pin. The square wave amplitude should have val
-
leys that are below 0.4V and peaks above 2.0V (up to 6V).
The
LT8612 will not enter Burst Mode operation at low
output loads while synchronized to an external clock, but
instead will pulse skip to maintain
regulation. The LT8612
may be synchronized over a 200kHz to 2.2MHz range. The
R
T
resistor should be chosen to set the LT8612 switching
frequency equal to or below the lowest synchronization
input. For example, if the synchronization signal will be
500kHz and higher, the R
T
should be selected for 500kHz.
The slope compensation is set by the R
T
value, while the
minimum slope compensation required to avoid subhar-
monic oscillations
is established by the inductor size,
input voltage, and output voltage. Since the synchroniza-
tion frequency
will not change the slopes of the inductor
current waveform, if the inductor is large enough to avoid
subharmonic oscillations at the frequency set by R
T
, then
the slope compensation will be sufficient for all synchro-
nization frequencies.
For
some applications it is desirable for the LT8612 to
operate in pulse-skipping mode, offering two major differ
-
ences from Burst Mode operation. First is the clock stays
awake at all times and all switching cycles are aligned to
the clock. Second is that full switching frequency is reached
at lower output load than in Burst Mode operation. These
two differences come at the expense of increased quiescent
current. To enable
pulse-skipping mode, the SYNC pin is
tied high either to a logic output or to the INT
VCC pin.
The LT8612 does not operate in forced continuous mode
regardless of SYNC signal. Never leave the SYNC pin
floating.
Shorted and Reversed Input Protection
The LT8612 will tolerate a shorted output. Several features
are used for protection during output short-circuit and
brownout conditions. The first is the switching frequency
will be folded back while the output is lower than the set
point to maintain inductor current control. Second, the
bottom switch current is monitored such that if inductor
current is beyond safe levels switching of the top switch
will be delayed until such time as the inductor current
falls to safe levels.
Frequency foldback behavior depends on the state of the
SYNC pin: If the SYNC pin is low the switching frequency
will slow while the output voltage is lower than the pro
-
grammed level. If the SYNC pin is connected to a clock
source or tied high, the LT8612 will stay at the programmed
frequency without foldback and only slow switching if the
inductor current exceeds safe levels.
There is another situation to consider in systems where
the
output will be held high when the input to the LT8612
is
absent. This may occur in battery charging applications
or in battery-backup systems where a battery or some
other supply is diode ORed with the LT8612’s output. If
the V
IN
pin is allowed to float and the EN pin is held high
(either by a logic signal or because it is tied to V
IN
), then
the LT8612’s internal circuitry will pull its quiescent current
through its SW pin. This is acceptable if the system can
tolerate several μA in this state. If the EN pin is grounded
the SW pin current will drop to nearA. However, if the
V
IN
pin is grounded while the output is held high, regard-
less of EN, parasitic body diodes inside the LT8612 can
pull
current from the output through the SW pin and
the V
IN
pin. Figure 3 shows a connection of the V
IN
and
EN/UV pins that will allow the LT8612 to run only when
the
input voltage is present and that protects against a
shorted or reversed input.
LT8612
17
8612f
For more information www.linear.com/LT8612
applicaTions inForMaTion
Figure 3. Reverse V
IN
Protection
Figure 4. Recommended PCB Layout for the LT8612
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 4 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
flow in the LT8612’s V
IN
pins, PGND pins, and the input ca-
pacitor (C1). The loop
formed by the input capacitor should
be as small as possible by placing the capacitor adjacent
to the V
IN
and PGND pins. When using a physically large
input capacitor the resulting loop may become too large
in which case using a small case/value capacitor placed
close to the V
IN
and PGND pins plus a larger capacitor
further away is preferred. These components, along with
the inductor and output capacitor, should be placed on the
same side of the circuit board, and their connections should
be made on that layer. Place a local, unbroken ground
plane under the application circuit on the layer closest to
the surface layer. The SW and BOOST nodes should be
as small as possible. Finally, keep the FB and RT nodes
small so that the ground traces will
shield them from the
SW
and BOOST nodes. The exposed pad on the bottom of
the package must be soldered to ground so that the pad
is connected to ground electrically and also acts as a heat
sink thermally. To keep thermal resistance low, extend the
ground plane as much as possible, and add thermal vias
under and near the LT8612 to additional ground planes
within the circuit board and on the bottom side.
High Temperature Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT8612. The exposed pad on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread heat dissipated by the LT8612.
Placing additional vias can reduce thermal resistance
further. The maximum load current should be derated
as the ambient temperature approaches the maximum
junction rating. Power dissipation within the LT8612 can
be estimated by calculating the total power loss from an
efficiency measurement and subtracting the inductor loss.
The die temperature is calculated by multiplying the LT8612
power dissipation by the thermal
resistance from junction
to ambient. The LT8612 will stop switching and indicate
a fault condition if safe junction temperature is exceeded.
V
IN
V
IN
D1
LT8612
EN/UV
8612 F03
GND
V
OUT
8612 F04
OUTLINE OF LOCAL
GROUND PLANE
SW
BST
BIAS
INTV
CC
GND
17
16
15
18
19
20
21
22
23 PG
FB
GND
V
OUT
24
SYNC
TR/SS
RT
EN/UV
V
IN
1
2
3
4
5
6
7
8
9
10
11 12 13 14
28 27 26 25
V
OUT
LINE TO BIAS VIAS TO GROUND PLANE
LT8612
18
8612f
For more information www.linear.com/LT8612
Typical applicaTions
5V Step-Down Converter
3.3V Step-Down Converter
5V Step-Down Converter 1.8V 2MHz Step-Down Converter
3.3V Step-Down Converter
12V Step-Down Converter
Ultralow EMI 5V 6A Step-Down Converter
1.8V Step-Down Converter
BSTV
IN
EN/UV
SYNC
INTV
CC
TR/SS
RT
SW
LT8612
GND
PGND
BIAS
8612 TA02
PG
FB
0.1µF
V
OUT
5V
6A
4.7µF
V
IN
5.6V TO 42V
1µF
10nF
10pF
2.5µH
1M
243k
f
SW
= 2MHz
18.2k
47µF×2
1210
POWER GOOD
100k
BSTV
IN
EN/UV
SYNC
INTV
CC
TR/SS
RT
SW
LT8612
GND
PGND
BIAS
8612 TA03
PG
FB
0.1µF
V
OUT
5V
6A
4.7µF
V
IN
5.6V TO 42V
1µF
10nF
10pF
10µH
1M
243k
f
SW
= 400kHz
110k
47µF×2
1210
POWER GOOD
100k
BSTV
IN
EN/UV
SYNC
PG
INTV
CC
TR/SS
RT
SW
LT8612
GND
PGND
BIAS
8612 TA04
FB
0.1µF
V
OUT
3.3V
6A
4.7µF
V
IN
3.9V TO 27V
(42V TRANSIENT)
1µF
10nF
4.7pF
1.8µH
1M
412k
f
SW
= 2MHz
18.2k
47µF×2
1210
BSTV
IN
EN/UV
SYNC
PG
INTV
CC
TR/SS
RT
SW
LT8612
GND
PGND
BIAS
8612 TA06
FB
0.1µF
V
OUT
1.8V
6A
4.7µF
V
IN
3.4V TO 20V
(42V TRANSIENT)
1µF
10nF
4.7pF
1µH
866k
1M
f
SW
= 2MHz
18.2k
47µF×2
1210
BSTV
IN
EN/UV
SYNC
PG
INTV
CC
TR/SS
RT
SW
LT8612
GND
PGND
BIAS
8612 TA07
FB
0.1µF
V
OUT
1.8V
6A
4.7µF
V
IN
3.4V TO 42V
1µF
10nF
4.7pF
4.7µH
866k
1M
f
SW
= 400kHz
110k
47µF×3
1210
BSTV
IN
EN/UV
PG
SYNC
INTV
CC
TR/SS
RT
SW
LT8612
GND
PGND
BIAS
8612 TA11
FB
0.1µF
V
OUT
5V
6A
4.7µF
V
IN
6V TO 42V
1µF
10nF
10pF
4.7µH
4.7µH
1M
FB1
BEAD
FB1: TDK MPZ2012S221A
243k
f
SW
= 800kHz
52.3k
4.7µF4.7µF
47µF×2
1210
BSTV
IN
EN/UV
SYNC
PG
INTV
CC
TR/SS
RT
SW
LT8612
GND
PGND
BIAS
8612 TA05
FB
0.1µF
V
OUT
3.3V
6A
4.7µF
V
IN
3.9V TO 42V
1µF
10nF
4.7pF
8.2µH
1M
412k
f
SW
= 400kHz
110k
47µF×2
1210
BSTV
IN
EN/UV
SYNC
INTV
CC
TR/SS
RT
SW
LT8612
GND
PGND
BIAS
8612 TA09
PG
FB
0.1µF
V
OUT
12V
6A
4.7µF
V
IN
12.8V TO 42V
1µF
10nF
10pF
10µH
1M
88.7k
f
SW
= 1MHz
41.2k
47µF×2
1210
POWER GOOD
100k

LT8612EUDE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 42V, 6A Synchronous Step-Down Regulator with 2.5uA Quiescent Current
Lifecycle:
New from this manufacturer.
Delivery:
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