LTC4215/LTC4215-2
5
4215fe
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. V
DD
= 12V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specifi ed.
Note 3: An internal clamp limits the GATE pin to a minimum of 5V above
SOURCE. Driving this pin to voltages beyond the clamp may damage the device.
Note 4: Offset error is the offset voltage measured from 1LSB when the
output code fl ickers between 0000 0000 and 0000 0001.
Note 5: Integral nonlinearity is defi ned as the deviation of a code from a
precise analog input voltage. Maximum specifi cations are limited by the
LSB step size and the single shot measurement. Typical specifi cations are
measured from the 1/4, 1/2 and 3/4 areas of the quantization band.
Note 6: Guaranteed by design and not subject to test.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TUE Total Unadjusted Error V
DD
– SENSE
SOURCE
ADIN
l
l
l
±5.5
±5.0
±5.0
LSB
LSB
LSB
FSE Full-Scale Error V
DD
– SENSE
SOURCE
ADIN
l
l
l
±5.5
±5.0
±5.0
LSB
LSB
LSB
V
FS
Full-Scale Voltage (255 • V
LSB
)V
DD
– SENSE
SOURCE
ADIN
l
l
l
37.625
15.14
1.205
38.45
15.44
1.23
39.275
15.74
1.255
mV
V
V
R
ADIN
ADIN Pin Sampling Resistance V
ADIN
= 1.28V
l
12
MΩ
I
ADIN
ADIN Pin Input Current V
ADIN
= 1.28V
l
0
±0.1
µA
Conversion Rate 10 Hz
I
2
C Interface
V
ADR(H)
ADR0, ADR1, ADR2 Input High Voltage
l
INTV
CC
–0.8
INTV
CC
–0.4
INTV
CC
–0.2
V
I
ADR(IN,Z)
ADR0, ADR1, ADR2 Hi-Z Input Current ADR0, ADR1, ADR2 = 0.8V
ADR0, ADR1, ADR2 = INTV
CC
– 0.8V
l
l
3
–3 µA
µA
V
ADR(L)
ADR0, ADR1, ADR2 Input Low Voltage
l
0.2 0.4 0.8 V
I
ADR(IN)
ADR0, ADR1, ADR2 Input Current ADR0, ADR1, ADR2 = 0V, INTV
CC
l
–80 80 µA
I
ALERT
ALERT Input Current ALERT = 6.5V
l
±1 µA
V
ALERT(OL)
ALERT Output Low Voltage I
ALERT
= 3mA
l
0.2 0.4 V
V
SDA,SCL(TH)
SDA, SCL Input Threshold
l
1.3 1.7 1.9 V
I
SDA,SCL(OH)
SDA, SCL Input Current SCL, SDA = 6.5V
l
±1 µA
V
SDA(OL)
SDA Output Low Voltage I
SDA
= 3mA
l
0.2 0.4 V
I
2
C Interface Timing
f
SCL(MAX)
SCL Clock Frequency Operates with f
SCL
≤ f
SCL(MAX)
l
400 1000 kHz
t
BUF(MIN)
Bus Free Time Between Stop/Start Condition
l
0.12 1.3 µs
t
HD,STA(MIN)
Hold Time After (Repeated) Start Condition
l
30 600 ns
t
SU,STA(MIN)
Repeated Start Condition Set-Up Time
l
30 600 ns
t
SU,STO(MIN)
Stop Condition Set-Up Time
l
140 600 ns
t
HD,DAT(MIN)
Data Hold Time (Input)
l
30 100 ns
t
HD,DATO
Data Hold Time (Output)
l
300 500 900 ns
t
SU,DAT(MIN)
Data Set-Up Time
l
30 600 ns
t
SP
Suppressed Spike Pulse Width
l
50 110 250 ns
C
X
SCL, SDA Input Capacitance SDAI Tied to SDAO (Note 6)
l
10 pF
